top.vho

ddr2 controller功能控制,里面有四个模块

	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(21),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a21_a_areg0);

DQ_a6_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a6_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(6),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a6_a_areg0);

DQ_a3_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a3_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(3),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a3_a_areg0);

DQ_a33_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a33_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(33),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a33_a_areg0);

DQ_a30_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a30_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(30),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a30_a_areg0);

DQ_a24_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a24_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(24),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a24_a_areg0);

DQ_a2_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a2_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(2),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a2_a_areg0);

DQ_a1_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a1_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(1),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a1_a_areg0);

DQ_a27_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a27_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(27),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a27_a_areg0);

DQ_a25_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a25_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(25),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a25_a_areg0);

DQ_a32_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a32_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(32),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a32_a_areg0);

DQ_a18_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",