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📄 top.vho

📁 ddr2 controller功能控制,里面有四个模块
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	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a22_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(22),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a22_a_areg0);

DQ_a0_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a0_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(0),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a0_a_areg0);

DQ_a26_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a26_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(26),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a26_a_areg0);

DQ_a31_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a31_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(31),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a31_a_areg0);

DQ_a14_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a14_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(14),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a14_a_areg0);

DQ_a16_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a16_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(16),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a16_a_areg0);

DQ_a11_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a11_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(11),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a11_a_areg0);

DQ_a9_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a9_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(9),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a9_a_areg0);

DQ_a35_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a35_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(35),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a35_a_areg0);

DQ_a10_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a10_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(10),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a10_a_areg0);

DQ_a21_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a21_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
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