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ddr2 controller功能控制,里面有四个模块

SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a16_a : std_logic;
SIGNAL DATA_IN_a11_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a11_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a11_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a11_a : std_logic;
SIGNAL DATA_IN_a9_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a9_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a9_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a9_a : std_logic;
SIGNAL DATA_IN_a35_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a35_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a35_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a35_a : std_logic;
SIGNAL DATA_IN_a10_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a10_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a10_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a10_a : std_logic;
SIGNAL DATA_IN_a21_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a21_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a21_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a21_a : std_logic;
SIGNAL DATA_IN_a6_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a6_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a6_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a6_a : std_logic;
SIGNAL DATA_IN_a3_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a3_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a3_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a3_a : std_logic;
SIGNAL DATA_IN_a33_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a33_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a33_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a33_a : std_logic;
SIGNAL DATA_IN_a30_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a30_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a30_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a30_a : std_logic;
SIGNAL DATA_IN_a24_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a24_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a24_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a24_a : std_logic;
SIGNAL DATA_IN_a2_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a2_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a2_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a2_a : std_logic;
SIGNAL DATA_IN_a1_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a1_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a1_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a1_a : std_logic;
SIGNAL DATA_IN_a27_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a27_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a27_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a27_a : std_logic;
SIGNAL DATA_IN_a25_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a25_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a25_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a25_a : std_logic;
SIGNAL DATA_IN_a32_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a32_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a32_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a32_a : std_logic;
SIGNAL DATA_IN_a18_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a18_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a18_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a18_a : std_logic;
SIGNAL DATA_IN_a15_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a15_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a15_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a15_a : std_logic;
SIGNAL DATA_IN_a29_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a29_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a29_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a29_a : std_logic;
SIGNAL DATA_IN_a12_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a12_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a12_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a12_a : std_logic;
SIGNAL DATA_IN_a8_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a8_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a8_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a8_a : std_logic;
SIGNAL DATA_IN_a20_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a20_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a20_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a20_a : std_logic;
SIGNAL DATA_IN_a7_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a7_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a7_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a7_a : std_logic;
SIGNAL DATA_IN_a17_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a17_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a17_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a17_a : std_logic;
SIGNAL DATA_IN_a13_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a13_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a13_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a13_a : std_logic;
SIGNAL DATA_IN_a5_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a5_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a5_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a5_a : std_logic;
SIGNAL DATA_IN_a4_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a4_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a4_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a4_a : std_logic;
SIGNAL DATA_IN_a19_a_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_in_reg_a19_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a0_a_a19_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a19_a : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a35_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a34_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a33_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a32_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a31_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a30_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a29_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a28_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a27_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a26_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a25_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a24_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a23_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a22_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a21_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a20_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a19_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a18_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a17_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a16_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a15_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a14_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a13_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a12_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a11_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a10_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a9_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a8_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a7_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a6_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a5_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a4_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a3_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a2_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a1_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_adata_out_reg_a0_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a16_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a16_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a15_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a15_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a14_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a14_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a13_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a13_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a12_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a12_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a11_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a11_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a10_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a10_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a9_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a9_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a8_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a8_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a7_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a7_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a6_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a6_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a5_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a5_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a4_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a4_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a3_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a3_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a2_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a2_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a1_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a1_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_reg_a0_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_addr_a0_a_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_rw_n_areg0 : std_logic;
SIGNAL ADDR_ADV_LD_N_acombout : std_logic;
SIGNAL zbt_ctrl_top_inst1_apipe_stage1_aaddr_adv_ld_n_reg_areg0 : std_logic;
SIGNAL zbt_ctrl_top_inst1_aaddr_ctrl_out1_aram_adv_ld_n_areg0 : std_logic;
SIGNAL NOT_zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a3_a_areg0 : std_logic;
SIGNAL NOT_zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a2_a_areg0 : std_logic;
SIGNAL NOT_zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a1_a_areg0 : std_logic;
SIGNAL NOT_zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a0_a_areg0 : std_logic;
SIGNAL NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a : std_logic;
SIGNAL NOT_RESET_N_acombout : std_logic;

BEGIN

ww_RESET_N <= RESET_N;
ww_clk <= clk;
ww_ADDR <= ADDR;
ww_RD_WR_N <= RD_WR_N;
ww_ADDR_ADV_LD_N <= ADDR_ADV_LD_N;
ww_DM <= DM;
ww_DATA_IN <= DATA_IN;
DATA_OUT <= ww_DATA_OUT;
SA <= ww_SA;
RW_N <= ww_RW_N;
ADV_LD_N <= ww_ADV_LD_N;
BW_N <= ww_BW_N;

ww_PLL1_inst_aaltpll_component_apll_inclk <= (gnd & clk_acombout);

PLL1_inst_aaltpll_component_a_clk0 <= ww_PLL1_inst_aaltpll_component_apll_clk(0);
PLL1_inst_aaltpll_component_apll_aCLK1 <= ww_PLL1_inst_aaltpll_component_apll_clk(1);
PLL1_inst_aaltpll_component_apll_aCLK2 <= ww_PLL1_inst_aaltpll_component_apll_clk(2);
PLL1_inst_aaltpll_component_apll_aCLK3 <= ww_PLL1_inst_aaltpll_component_apll_clk(3);
PLL1_inst_aaltpll_component_apll_aCLK4 <= ww_PLL1_inst_aaltpll_component_apll_clk(4);
PLL1_inst_aaltpll_component_apll_aCLK5 <= ww_PLL1_inst_aaltpll_component_apll_clk(5);
NOT_zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a3_a_areg0 <= NOT zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a3_a_areg0;
NOT_zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a2_a_areg0 <= NOT zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a2_a_areg0;
NOT_zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a1_a_areg0 <= NOT zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a1_a_areg0;
NOT_zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a0_a_areg0 <= NOT zbt_ctrl_top_inst1_apipe_stage1_adm_reg_a0_a_areg0;
NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a <= NOT zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a;
NOT_RESET_N_acombout <= NOT RESET_N_acombout;

DQ_a34_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a34_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(34),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a34_a_areg0);

DQ_a28_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a28_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(28),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a28_a_areg0);

DQ_a23_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",
	input_sync_reset => "none",
	output_sync_reset => "none",
	oe_sync_reset => "none",
	input_power_up => "low",
	output_power_up => "low",
	oe_power_up => "low")
-- pragma translate_on
PORT MAP (
	datain => zbt_ctrl_top_inst1_apipe_delay1_adata_in_pipe_a1_a_a23_a,
	oe => NOT_zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a1_a,
	outclk => PLL1_inst_aaltpll_component_a_clk0,
	inclk => PLL1_inst_aaltpll_component_a_clk0,
	inclkena => zbt_ctrl_top_inst1_apipe_delay1_arw_n_pipe_a2_a,
	areset => NOT_RESET_N_acombout,
	devclrn => devclrn,
	devpor => devpor,
	devoe => devoe,
	padio => DQ(23),
	regout => zbt_ctrl_top_inst1_apipe_delay1_alb_data_out_a23_a_areg0);

DQ_a22_a_aI : stratix_io 
-- pragma translate_off
GENERIC MAP (
	operation_mode => "bidir",
	ddio_mode => "none",
	input_register_mode => "register",
	output_register_mode => "register",
	oe_register_mode => "register",
	input_async_reset => "clear",
	output_async_reset => "clear",
	oe_async_reset => "clear",