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📁 ddr2 controller功能控制,里面有四个模块
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        (PORT areset (2966:2966:2966) (2966:2966:2966) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a25_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1792:1792:1792) (1792:1792:1792) )
        (PORT clk (1620:1620:1620) (1620:1620:1620) )
        (PORT areset (2947:2947:2947) (2947:2947:2947) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a25_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a32_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1674:1674:1674) (1674:1674:1674) )
        (PORT ena (3013:3013:3013) (3013:3013:3013) )
        (PORT areset (3084:3084:3084) (3084:3084:3084) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a32_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1400:1400:1400) (1400:1400:1400) )
        (PORT clk (1577:1577:1577) (1577:1577:1577) )
        (PORT areset (3099:3099:3099) (3099:3099:3099) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a32_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2507:2507:2507) (2507:2507:2507) )
        (PORT clk (1620:1620:1620) (1620:1620:1620) )
        (PORT areset (3080:3080:3080) (3080:3080:3080) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a32_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a18_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1716:1716:1716) (1716:1716:1716) )
        (PORT ena (3013:3013:3013) (3013:3013:3013) )
        (PORT areset (3084:3084:3084) (3084:3084:3084) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a18_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1401:1401:1401) (1401:1401:1401) )
        (PORT clk (1577:1577:1577) (1577:1577:1577) )
        (PORT areset (3099:3099:3099) (3099:3099:3099) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a18_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2507:2507:2507) (2507:2507:2507) )
        (PORT clk (1620:1620:1620) (1620:1620:1620) )
        (PORT areset (3080:3080:3080) (3080:3080:3080) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a18_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a15_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1716:1716:1716) (1716:1716:1716) )
        (PORT ena (3013:3013:3013) (3013:3013:3013) )
        (PORT areset (3084:3084:3084) (3084:3084:3084) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a15_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1418:1418:1418) (1418:1418:1418) )
        (PORT clk (1577:1577:1577) (1577:1577:1577) )
        (PORT areset (3099:3099:3099) (3099:3099:3099) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a15_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2507:2507:2507) (2507:2507:2507) )
        (PORT clk (1620:1620:1620) (1620:1620:1620) )
        (PORT areset (3080:3080:3080) (3080:3080:3080) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a15_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a29_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1674:1674:1674) (1674:1674:1674) )
        (PORT ena (3013:3013:3013) (3013:3013:3013) )
        (PORT areset (3084:3084:3084) (3084:3084:3084) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a29_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1395:1395:1395) (1395:1395:1395) )
        (PORT clk (1577:1577:1577) (1577:1577:1577) )
        (PORT areset (3099:3099:3099) (3099:3099:3099) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a29_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2507:2507:2507) (2507:2507:2507) )
        (PORT clk (1620:1620:1620) (1620:1620:1620) )
        (PORT areset (3080:3080:3080) (3080:3080:3080) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a29_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a12_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1716:1716:1716) (1716:1716:1716) )
        (PORT ena (2934:2934:2934) (2934:2934:2934) )
        (PORT areset (3025:3025:3025) (3025:3025:3025) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a12_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1393:1393:1393) (1393:1393:1393) )
        (PORT clk (1577:1577:1577) (1577:1577:1577) )
        (PORT areset (3040:3040:3040) (3040:3040:3040) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a12_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2434:2434:2434) (2434:2434:2434) )
        (PORT clk (1620:1620:1620) (1620:1620:1620) )
        (PORT areset (3021:3021:3021) (3021:3021:3021) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a12_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a8_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1674:1674:1674) (1674:1674:1674) )
        (PORT ena (2934:2934:2934) (2934:2934:2934) )
        (PORT areset (3025:
上一页 1 2 3 45
💿 文件大小 1650 K
👤 上传用户 novelty1234
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#controller #ddr2 #控制 #模块
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