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📁 ddr2 controller功能控制,里面有四个模块
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        (PORT areset (2879:2879:2879) (2879:2879:2879) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a33_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1678:1678:1678) (1678:1678:1678) )
        (IOPATH datain padio (2142:2142:2142) (2142:2142:2142) )
        (IOPATH (posedge oe) padio (636:636:636) (636:636:636) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a30_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1100:1100:1100) (1100:1100:1100) )
        (PORT clk (1612:1612:1612) (1612:1612:1612) )
        (PORT ena (2817:2817:2817) (2817:2817:2817) )
        (PORT areset (2893:2893:2893) (2893:2893:2893) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a30_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1078:1078:1078) (1078:1078:1078) )
        (PORT clk (1562:1562:1562) (1562:1562:1562) )
        (PORT areset (2863:2863:2863) (2863:2863:2863) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a30_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2260:2260:2260) (2260:2260:2260) )
        (PORT clk (1627:1627:1627) (1627:1627:1627) )
        (PORT areset (2879:2879:2879) (2879:2879:2879) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a30_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1678:1678:1678) (1678:1678:1678) )
        (IOPATH datain padio (2142:2142:2142) (2142:2142:2142) )
        (IOPATH (posedge oe) padio (636:636:636) (636:636:636) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a24_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1100:1100:1100) (1100:1100:1100) )
        (PORT clk (1612:1612:1612) (1612:1612:1612) )
        (PORT ena (2817:2817:2817) (2817:2817:2817) )
        (PORT areset (2893:2893:2893) (2893:2893:2893) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a24_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1095:1095:1095) (1095:1095:1095) )
        (PORT clk (1562:1562:1562) (1562:1562:1562) )
        (PORT areset (2863:2863:2863) (2863:2863:2863) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a24_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2260:2260:2260) (2260:2260:2260) )
        (PORT clk (1627:1627:1627) (1627:1627:1627) )
        (PORT areset (2879:2879:2879) (2879:2879:2879) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a24_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1678:1678:1678) (1678:1678:1678) )
        (IOPATH datain padio (2142:2142:2142) (2142:2142:2142) )
        (IOPATH (posedge oe) padio (636:636:636) (636:636:636) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a2_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1716:1716:1716) (1716:1716:1716) )
        (PORT ena (1915:1915:1915) (1915:1915:1915) )
        (PORT areset (2939:2939:2939) (2939:2939:2939) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a2_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1367:1367:1367) (1367:1367:1367) )
        (PORT clk (1577:1577:1577) (1577:1577:1577) )
        (PORT areset (2954:2954:2954) (2954:2954:2954) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a2_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1797:1797:1797) (1797:1797:1797) )
        (PORT clk (1620:1620:1620) (1620:1620:1620) )
        (PORT areset (2935:2935:2935) (2935:2935:2935) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a2_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a1_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1716:1716:1716) (1716:1716:1716) )
        (PORT ena (1946:1946:1946) (1946:1946:1946) )
        (PORT areset (2932:2932:2932) (2932:2932:2932) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a1_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1397:1397:1397) (1397:1397:1397) )
        (PORT clk (1577:1577:1577) (1577:1577:1577) )
        (PORT areset (2947:2947:2947) (2947:2947:2947) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a1_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1824:1824:1824) (1824:1824:1824) )
        (PORT clk (1620:1620:1620) (1620:1620:1620) )
        (PORT areset (2928:2928:2928) (2928:2928:2928) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a1_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a27_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1674:1674:1674) (1674:1674:1674) )
        (PORT ena (1978:1978:1978) (1978:1978:1978) )
        (PORT areset (2919:2919:2919) (2919:2919:2919) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a27_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1393:1393:1393) (1393:1393:1393) )
        (PORT clk (1577:1577:1577) (1577:1577:1577) )
        (PORT areset (2934:2934:2934) (2934:2934:2934) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a27_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1848:1848:1848) (1848:1848:1848) )
        (PORT clk (1620:1620:1620) (1620:1620:1620) )
        (PORT areset (2915:2915:2915) (2915:2915:2915) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a27_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a25_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1674:1674:1674) (1674:1674:1674) )
        (PORT ena (1870:1870:1870) (1870:1870:1870) )
        (PORT areset (2951:2951:2951) (2951:2951:2951) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a25_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1398:1398:1398) (1398:1398:1398) )
        (PORT clk (1577:1577:1577) (1577:1577:1577) )
💿 文件大小 1650 K
👤 上传用户 novelty1234
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#controller #ddr2 #控制 #模块
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