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📁 ddr2 controller功能控制,里面有四个模块
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        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a35_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1737:1737:1737) (1737:1737:1737) )
        (PORT ena (2475:2475:2475) (2475:2475:2475) )
        (PORT areset (2978:2978:2978) (2978:2978:2978) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a35_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1394:1394:1394) (1394:1394:1394) )
        (PORT clk (1598:1598:1598) (1598:1598:1598) )
        (PORT areset (2993:2993:2993) (2993:2993:2993) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a35_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2520:2520:2520) (2520:2520:2520) )
        (PORT clk (1641:1641:1641) (1641:1641:1641) )
        (PORT areset (2974:2974:2974) (2974:2974:2974) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a35_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a10_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1737:1737:1737) (1737:1737:1737) )
        (PORT ena (2475:2475:2475) (2475:2475:2475) )
        (PORT areset (2978:2978:2978) (2978:2978:2978) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a10_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1396:1396:1396) (1396:1396:1396) )
        (PORT clk (1598:1598:1598) (1598:1598:1598) )
        (PORT areset (2993:2993:2993) (2993:2993:2993) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a10_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2520:2520:2520) (2520:2520:2520) )
        (PORT clk (1641:1641:1641) (1641:1641:1641) )
        (PORT areset (2974:2974:2974) (2974:2974:2974) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a10_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a21_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1737:1737:1737) (1737:1737:1737) )
        (PORT ena (2475:2475:2475) (2475:2475:2475) )
        (PORT areset (2978:2978:2978) (2978:2978:2978) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a21_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1396:1396:1396) (1396:1396:1396) )
        (PORT clk (1598:1598:1598) (1598:1598:1598) )
        (PORT areset (2993:2993:2993) (2993:2993:2993) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a21_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2520:2520:2520) (2520:2520:2520) )
        (PORT clk (1641:1641:1641) (1641:1641:1641) )
        (PORT areset (2974:2974:2974) (2974:2974:2974) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a21_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a6_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1695:1695:1695) (1695:1695:1695) )
        (PORT ena (2339:2339:2339) (2339:2339:2339) )
        (PORT areset (3022:3022:3022) (3022:3022:3022) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a6_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1390:1390:1390) (1390:1390:1390) )
        (PORT clk (1598:1598:1598) (1598:1598:1598) )
        (PORT areset (3037:3037:3037) (3037:3037:3037) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a6_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2365:2365:2365) (2365:2365:2365) )
        (PORT clk (1641:1641:1641) (1641:1641:1641) )
        (PORT areset (3018:3018:3018) (3018:3018:3018) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a6_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (2260:2260:2260) (2260:2260:2260) )
        (IOPATH datain padio (2715:2715:2715) (2715:2715:2715) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a3_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1100:1100:1100) (1100:1100:1100) )
        (PORT clk (1612:1612:1612) (1612:1612:1612) )
        (PORT ena (2817:2817:2817) (2817:2817:2817) )
        (PORT areset (2893:2893:2893) (2893:2893:2893) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a3_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1077:1077:1077) (1077:1077:1077) )
        (PORT clk (1562:1562:1562) (1562:1562:1562) )
        (PORT areset (2863:2863:2863) (2863:2863:2863) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a3_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2260:2260:2260) (2260:2260:2260) )
        (PORT clk (1627:1627:1627) (1627:1627:1627) )
        (PORT areset (2879:2879:2879) (2879:2879:2879) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a3_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1678:1678:1678) (1678:1678:1678) )
        (IOPATH datain padio (2142:2142:2142) (2142:2142:2142) )
        (IOPATH (posedge oe) padio (636:636:636) (636:636:636) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a33_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1100:1100:1100) (1100:1100:1100) )
        (PORT clk (1612:1612:1612) (1612:1612:1612) )
        (PORT ena (2817:2817:2817) (2817:2817:2817) )
        (PORT areset (2893:2893:2893) (2893:2893:2893) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a33_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1078:1078:1078) (1078:1078:1078) )
        (PORT clk (1562:1562:1562) (1562:1562:1562) )
        (PORT areset (2863:2863:2863) (2863:2863:2863) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a33_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2260:2260:2260) (2260:2260:2260) )
        (PORT clk (1627:1627:1627) (1627:1627:1627) )
💿 文件大小 1650 K
👤 上传用户 novelty1234
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#controller #ddr2 #控制 #模块
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