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📁 ddr2 controller功能控制,里面有四个模块
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      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a26_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1371:1371:1371) (1371:1371:1371) )
        (PORT clk (1598:1598:1598) (1598:1598:1598) )
        (PORT areset (3037:3037:3037) (3037:3037:3037) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a26_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2388:2388:2388) (2388:2388:2388) )
        (PORT clk (1641:1641:1641) (1641:1641:1641) )
        (PORT areset (3018:3018:3018) (3018:3018:3018) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a26_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (2260:2260:2260) (2260:2260:2260) )
        (IOPATH datain padio (2715:2715:2715) (2715:2715:2715) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a31_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1695:1695:1695) (1695:1695:1695) )
        (PORT ena (2450:2450:2450) (2450:2450:2450) )
        (PORT areset (2989:2989:2989) (2989:2989:2989) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a31_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1395:1395:1395) (1395:1395:1395) )
        (PORT clk (1598:1598:1598) (1598:1598:1598) )
        (PORT areset (3004:3004:3004) (3004:3004:3004) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a31_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2494:2494:2494) (2494:2494:2494) )
        (PORT clk (1641:1641:1641) (1641:1641:1641) )
        (PORT areset (2985:2985:2985) (2985:2985:2985) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a31_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a14_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1695:1695:1695) (1695:1695:1695) )
        (PORT ena (2450:2450:2450) (2450:2450:2450) )
        (PORT areset (2989:2989:2989) (2989:2989:2989) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a14_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1395:1395:1395) (1395:1395:1395) )
        (PORT clk (1598:1598:1598) (1598:1598:1598) )
        (PORT areset (3004:3004:3004) (3004:3004:3004) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a14_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2494:2494:2494) (2494:2494:2494) )
        (PORT clk (1641:1641:1641) (1641:1641:1641) )
        (PORT areset (2985:2985:2985) (2985:2985:2985) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a14_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a16_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1695:1695:1695) (1695:1695:1695) )
        (PORT ena (2394:2394:2394) (2394:2394:2394) )
        (PORT areset (3028:3028:3028) (3028:3028:3028) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a16_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1393:1393:1393) (1393:1393:1393) )
        (PORT clk (1598:1598:1598) (1598:1598:1598) )
        (PORT areset (3043:3043:3043) (3043:3043:3043) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a16_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2431:2431:2431) (2431:2431:2431) )
        (PORT clk (1641:1641:1641) (1641:1641:1641) )
        (PORT areset (3024:3024:3024) (3024:3024:3024) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a16_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a11_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1695:1695:1695) (1695:1695:1695) )
        (PORT ena (2394:2394:2394) (2394:2394:2394) )
        (PORT areset (3028:3028:3028) (3028:3028:3028) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a11_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1393:1393:1393) (1393:1393:1393) )
        (PORT clk (1598:1598:1598) (1598:1598:1598) )
        (PORT areset (3043:3043:3043) (3043:3043:3043) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a11_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2431:2431:2431) (2431:2431:2431) )
        (PORT clk (1641:1641:1641) (1641:1641:1641) )
        (PORT areset (3024:3024:3024) (3024:3024:3024) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a11_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
        (IOPATH (posedge oe) padio (522:522:522) (522:522:522) )
        (IOPATH (negedge oe) padio (0:0:0) (0:0:0) )
        (IOPATH regin regout (0:0:0) (0:0:0) )
      )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a9_a_aI.in_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (978:978:978) (978:978:978) )
        (PORT clk (1695:1695:1695) (1695:1695:1695) )
        (PORT ena (2427:2427:2427) (2427:2427:2427) )
        (PORT areset (2988:2988:2988) (2988:2988:2988) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
      (SETUP ena (posedge clk) (276:276:276) )
      (HOLD ena (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a9_a_aI.out_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (1394:1394:1394) (1394:1394:1394) )
        (PORT clk (1598:1598:1598) (1598:1598:1598) )
        (PORT areset (3003:3003:3003) (3003:3003:3003) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_io_register" )
    (INSTANCE DQ_a9_a_aI.oe_reg )
    (DELAY
      (ABSOLUTE
        (PORT datain (2466:2466:2466) (2466:2466:2466) )
        (PORT clk (1641:1641:1641) (1641:1641:1641) )
        (PORT areset (2984:2984:2984) (2984:2984:2984) )
        (IOPATH (posedge clk) regout (162:162:162) (162:162:162) )
        (IOPATH (posedge areset) regout (280:280:280) (280:280:280) )
      )
    )
    (TIMINGCHECK
      (SETUP datain (posedge clk) (276:276:276) )
      (HOLD datain (posedge clk) (64:64:64) )
    )
  )
  (CELL
    (CELLTYPE "stratix_asynch_io" )
    (INSTANCE DQ_a9_a_aI.inst1 )
    (DELAY
      (ABSOLUTE
        (PORT oe (1990:1990:1990) (1990:1990:1990) )
        (IOPATH datain padio (2445:2445:2445) (2445:2445:2445) )
💿 文件大小 1650 K
👤 上传用户 novelty1234
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#controller #ddr2 #控制 #模块
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