1.txt

VHDL router16通路选择器 基于实际模型的设计

module router(dout,nFrameo,nValido,address,
       din, nFrame, nValid,clk, nRst);
output reg dout;
output reg nFrameo;
output reg nValido;
output reg [3:0]address;
input  din, nFrame, nValid;
input clk, nRst;

parameter Idle_state=0, Addr_state=1, Data_state=2;
reg [1:0]state;
reg [1:0]next_state;
reg [8:0]shifter;
reg [3:0]bitCounter;

always @(posedge clk or nRst)
  if(!nRst) 
           begin
            dout<=0;
            nFrameo<=0;
            nValido<=0;
            state<=0;
            shifter<=0;
            bitCounter<=0;
           end
  else      state<=next_state;
           
always @(posedge clk)         
           case(state)
            Idle_state: //Idle_state
                begin
                 if(!nFrame) next_state<=Addr_state;
                 else next_state<=Idle_state;
                 nFrameo<=1;
                 nValido<=1; 
                 bitCounter<=0;              
                end 
            Addr_state: //Addr_state
                begin
                 if(bitCounter==9) next_state<=Data_state; 
                 else 
                   begin
                    bitCounter<=bitCounter+1;
                    next_state<=Addr_state;
                    shifter<={shifter[7:0],din};
                   end
                end
             Data_state: //Data_state
               begin
                if(nFrame==1)  next_state<=Idle_state;
                else next_state<=Data_state;
                dout<=din;
                address<=shifter[3:0];
                nValido<=nValid;
                nFrameo<=0;
               end   
             default: next_state<=Idle_state; 
          endcase            
         
endmodule