⭐ 欢迎来到虫虫下载站! | 📦 资源下载 📁 资源专辑 ℹ️ 关于我们
⭐ 虫虫下载站

📄 d__program_fpga_software_modelsim_xilinx_lib_xilinxcorelib_ver__info

📁 使用VERILOG实现QPSK信号的匹配滤波
💻
📖 第 1 页 / 共 5 页
字号:
31o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k_@m@e@m_@g@e@n_@v2_6_output_stagevBLK_MEM_GEN_V2_6_xstI92ZZcPKNiOlLP[b1QO?jf1VK`UzoM__:hGi=Dlg:0:5B1dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 35680VK`UzoM__:hGi=Dlg:0:5B1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k_@m@e@m_@g@e@n_@v2_6_xstvBLK_MEM_GEN_V2_7I<6LA^_IF2m]GIWlQjO:la0VT8S[z63j0;mcL]01aezA53dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 13234VT8S[z63j0;mcL]01aezA53OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k_@m@e@m_@g@e@n_@v2_7vBLK_MEM_GEN_V2_7_output_stageIg6z7BbTjzN5M1L8Qc8GP@3VZ46EOc9M:TU;U5iO9B;md1dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 13059VZ46EOc9M:TU;U5iO9B;md1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k_@m@e@m_@g@e@n_@v2_7_output_stagevBLK_MEM_GEN_V2_7_xstI5enlZMOndG@6aRNX@88jE0VUk24U`A;R@jORCmaQFa<J3dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 14305VUk24U`A;R@jORCmaQFa<J3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k_@m@e@m_@g@e@n_@v2_7_xstvBLKMEMDP_V3_2IMLhkQ7^_@dEmG]OhlmFUZ2Vfja]1hZU2DEzBg9DcNfLZ0dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 98392Vfja]1hZU2DEzBg9DcNfLZ0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@d@p_@v3_2vBLKMEMDP_V4_0IT^@N5mTn;QP<QLdJAfzc@0V4HfiGLo42U;gZc[B0nYUH1dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 90899V4HfiGLo42U;gZc[B0nYUH1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@d@p_@v4_0vBLKMEMDP_V5_0IaTb]m<Z1>[O1i?IiYZ@982V=f;gEFXFLGBeiHn^Q@HTf3dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 115419V=f;gEFXFLGBeiHn^Q@HTf3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@d@p_@v5_0vBLKMEMDP_V6_0IcmmmY_6mz]b7^iEzUdDE`0VJ^lOOSLYHPAaNGD@2chaP0dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 102185VJ^lOOSLYHPAaNGD@2chaP0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@d@p_@v6_0vBLKMEMDP_V6_1I;eh@=lJjKBB88QZUXJ]fn0Vj217gOT0]UFTH98l9dSm92dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 100359Vj217gOT0]UFTH98l9dSm92OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@d@p_@v6_1vBLKMEMDP_V6_2IzN90EdOj_X7G3XBe3MQW]2VIREVV<Jf]7G8_JGe@@N@F2dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 65392VIREVV<Jf]7G8_JGe@@N@F2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@d@p_@v6_2vBLKMEMDP_V6_3I@gPdfE=;P2YFkJ?4n;MX:2V<HJR[8M_l_ZP=zFdfL=VH2dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 64075V<HJR[8M_l_ZP=zFdfL=VH2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@d@p_@v6_3vBLKMEMSP_V3_2I;lVP<`KI9P2zl]aHZT58>1VeoGhXWcg@`CHS:B_5JVXC3dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 101654VeoGhXWcg@`CHS:B_5JVXC3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@s@p_@v3_2vBLKMEMSP_V4_0InHm`>bPi5BOfQC4kn[z:j1Vao;S=OmiB?^o_eMg[9d1i1dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 117829Vao;S=OmiB?^o_eMg[9d1i1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@s@p_@v4_0vBLKMEMSP_V5_0IA_OTK09i2L58AEeQj2Rh40VoK[=D<_8;1FGcJinG1kWb0dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 103479VoK[=D<_8;1FGcJinG1kWb0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@s@p_@v5_0vBLKMEMSP_V6_0I@IdTiCfQdMZ:;`0HBDG5]0Vn]75z[KG?n8z:`[R^NB`R1dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 114907Vn]75z[KG?n8z:`[R^NB`R1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@s@p_@v6_0vBLKMEMSP_V6_1I@V1S?_z5WTWSM_Be:G]H@0VB@;H36m43=9fX=6B2QcL63dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 110296VB@;H36m43=9fX=6B2QcL63OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@s@p_@v6_1vBLKMEMSP_V6_2IdoYlji6nP7]GPN`KnLmEQ2Vg4KG1HB8KW>2j^DY_JMSe1dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 63534Vg4KG1HB8KW>2j^DY_JMSe1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@b@l@k@m@e@m@s@p_@v6_2vbutterflyIo>iL?3O<<cnho0FZPggb?0VC^M;mT9b5KcO4C]5lcOCS3dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 4639VC^M;mT9b5KcO4C]5lcOCS3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vervC_ACCUM_V2_0IE@JbUVTYDFC1GU5gRe_B=3VOD6YQG5^n<9_OL7M[_5[M0dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 124138VOD6YQG5^n<9_OL7M[_5[M0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@c@c@u@m_@v2_0vC_ACCUM_V3_0I37c_RV>YzRgbDN]`9282H1VKS;@zdB1N:akkfQ0>1dk=1dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 139283VKS;@zdB1N:akkfQ0>1dk=1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@c@c@u@m_@v3_0vC_ACCUM_V4_0I^QhoMV90ZgJd=g4PR;3h41Vn@@8nDZZ?b6]QP3C9j14[1dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 132448Vn@@8nDZZ?b6]QP3C9j14[1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@c@c@u@m_@v4_0vC_ACCUM_V5_0I4ek0J06XJ@@G1`WgFo47V3VcDMj_gM27z?S_>;AKLQI91dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 162274VcDMj_gM27z?S_>;AKLQI91OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@c@c@u@m_@v5_0vC_ACCUM_V5_1IRh5M3EkCd03?1O<Cho2SL0VR<mTDJT`5G1>8EPS[K7bE3dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 162928VR<mTDJT`5G1>8EPS[K7bE3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@c@c@u@m_@v5_1vC_ACCUM_V6_0IOWfd8U[lE^AXK@nIOQ6fO2V8]h2;BWg]KPVmNgeb=9DJ3dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 146957V8]h2;BWg]KPVmNgeb=9DJ3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@c@c@u@m_@v6_0vC_ACCUM_V7_0I5Nz>2VJ=XhZ<P7maO4N<12VDL0?GFW8=5`4PBU1`zDXE0dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 154402VDL0?GFW8=5`4PBU1`zDXE0OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@c@c@u@m_@v7_0vC_ADDSUB_V2_0IF?5g;heXiOW>0cmN4ZaUh3VcMfcYHb7N145S?ziK4S<U2dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 124763VcMfcYHb7N145S?ziK4S<U2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@d@d@s@u@b_@v2_0vC_ADDSUB_V3_0ITGXY0azzlQAEj0DL;h0^11VjI3JMJm?;@5PYAQ1oafQF3dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 139911VjI3JMJm?;@5PYAQ1oafQF3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@d@d@s@u@b_@v3_0vC_ADDSUB_V4_0IFFaBbBiSzaNam5gF=XXQM0VoZana7j1ZA`]iRZ@LR67=2dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 133076VoZana7j1ZA`]iRZ@LR67=2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@d@d@s@u@b_@v4_0vC_ADDSUB_V5_0I5G5UoHgCG4z<B:I[Vo>@a0V`bNfURO1:_cH<TcS^_:6?3dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 163583V`bNfURO1:_cH<TcS^_:6?3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@d@d@s@u@b_@v5_0vC_ADDSUB_V6_0I8cfgMANX@nB1O7kn9BK1O1V]7[@GXoAR?2lo5E>[e_@Z1dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 147620V]7[@GXoAR?2lo5E>[e_@Z1OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@d@d@s@u@b_@v6_0vC_ADDSUB_V7_0IEZck[31IZN<bUV:Pmen_D0VCVQ:aL1mHnbF28?o16dbf2dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 155095VCVQ:aL1mHnbF28?o16dbf2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@a@d@d@s@u@b_@v7_0vC_BIT_CORRELATOR_V3_0I0Vk5OKbB49YAm>@E6d[H`3V4_^[aS<07cY]bP@nXlOA<3dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 8082V4_^[aS<07cY]bP@nXlOA<3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@b@i@t_@c@o@r@r@e@l@a@t@o@r_@v3_0vC_CIC_V3_0IT5XHk7:QMdPmjYJLkzEUz0VgZYiPAfA_;[BYVHUbV==j3dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 6474VgZYiPAfA_;[BYVHUbV==j3OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@c@i@c_@v3_0vC_COMPARE_V2_0Il35zR>N[?kG;W2m;8VU]S3VLINMWUZWM5hX27^7=3?JM2dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 125378VLINMWUZWM5hX27^7=3?JM2OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@c@o@m@p@a@r@e_@v2_0vC_COMPARE_V3_0IAIhW>0X21^0nAka^8JL2K0VYYkHHcXmFjJoaJQ0a9mI02dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 140562VYYkHHcXmFjJoaJQ0a9mI02OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@c@o@m@p@a@r@e_@v3_0vC_COMPARE_V4_0I422HKRe0>ZPHK^mSP`QcO2Vc4Nk:UQKjkV`?Cc7QdgQ11dC:\Documents and Settings\userw1212132249FD:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_ver\XilinxCoreLib_ver_source.vL0 133727Vc4Nk:UQKjkV`?Cc7QdgQ11OE;L;6.2b;35r131o-source -93 -work D:\Program\FPGA_software\ModelSim\xilinx_lib\XilinxCoreLib_vern@c_@c@o@m@p@a@r@e_@v4_0

⌨️ 快捷键说明

复制代码 Ctrl + C
搜索代码 Ctrl + F
全屏模式 F11
切换主题 Ctrl + Shift + D
显示快捷键 ?
增大字号 Ctrl + =
减小字号 Ctrl + -