frequency.tan.qmsg

这个程序是基于等精度测频原理的频率计

{ "Info" "ITDB_TSU_RESULT" "qqq\[8\] start clk 4.756 ns register " "Info: tsu for register \"qqq\[8\]\" (data pin = \"start\", clock pin = \"clk\") is 4.756 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.640 ns + Longest pin register " "Info: + Longest pin to register delay is 7.640 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns start 1 PIN PIN_M1 94 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M1; Fanout = 94; PIN Node = 'start'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { start } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.275 ns) + CELL(0.183 ns) 5.183 ns qqq\[12\]~637 2 COMB LC_X45_Y13_N8 1 " "Info: 2: + IC(4.275 ns) + CELL(0.183 ns) = 5.183 ns; Loc. = LC_X45_Y13_N8; Fanout = 1; COMB Node = 'qqq\[12\]~637'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "4.458 ns" { start qqq[12]~637 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.478 ns) + CELL(0.280 ns) 5.941 ns qqq\[12\]~639 3 COMB LC_X46_Y13_N9 28 " "Info: 3: + IC(0.478 ns) + CELL(0.280 ns) = 5.941 ns; Loc. = LC_X46_Y13_N9; Fanout = 28; COMB Node = 'qqq\[12\]~639'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "0.758 ns" { qqq[12]~637 qqq[12]~639 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.994 ns) + CELL(0.705 ns) 7.640 ns qqq\[8\] 4 REG LC_X46_Y15_N9 4 " "Info: 4: + IC(0.994 ns) + CELL(0.705 ns) = 7.640 ns; Loc. = LC_X46_Y15_N9; Fanout = 4; REG Node = 'qqq\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "1.699 ns" { qqq[12]~639 qqq[8] } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.893 ns ( 24.78 % ) " "Info: Total cell delay = 1.893 ns ( 24.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.747 ns ( 75.22 % ) " "Info: Total interconnect delay = 5.747 ns ( 75.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "7.640 ns" { start qqq[12]~637 qqq[12]~639 qqq[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.640 ns" { start start~out0 qqq[12]~637 qqq[12]~639 qqq[8] } { 0.000ns 0.000ns 4.275ns 0.478ns 0.994ns } { 0.000ns 0.725ns 0.183ns 0.280ns 0.705ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" {  } { { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.894 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.894 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 115 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 115; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { clk } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.627 ns) + CELL(0.542 ns) 2.894 ns qqq\[8\] 2 REG LC_X46_Y15_N9 4 " "Info: 2: + IC(1.627 ns) + CELL(0.542 ns) = 2.894 ns; Loc. = LC_X46_Y15_N9; Fanout = 4; REG Node = 'qqq\[8\]'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.169 ns" { clk qqq[8] } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.78 % ) " "Info: Total cell delay = 1.267 ns ( 43.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.627 ns ( 56.22 % ) " "Info: Total interconnect delay = 1.627 ns ( 56.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.894 ns" { clk qqq[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.894 ns" { clk clk~out0 qqq[8] } { 0.000ns 0.000ns 1.627ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "7.640 ns" { start qqq[12]~637 qqq[12]~639 qqq[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "7.640 ns" { start start~out0 qqq[12]~637 qqq[12]~639 qqq[8] } { 0.000ns 0.000ns 4.275ns 0.478ns 0.994ns } { 0.000ns 0.725ns 0.183ns 0.280ns 0.705ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.894 ns" { clk qqq[8] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.894 ns" { clk clk~out0 qqq[8] } { 0.000ns 0.000ns 1.627ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk alarm1 alarm1~reg0 7.852 ns register " "Info: tco from clock \"clk\" to destination pin \"alarm1\" through register \"alarm1~reg0\" is 7.852 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.888 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.888 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns clk 1 CLK PIN_L2 115 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_L2; Fanout = 115; CLK Node = 'clk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { clk } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 9 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.621 ns) + CELL(0.542 ns) 2.888 ns alarm1~reg0 2 REG LC_X41_Y14_N0 2 " "Info: 2: + IC(1.621 ns) + CELL(0.542 ns) = 2.888 ns; Loc. = LC_X41_Y14_N0; Fanout = 2; REG Node = 'alarm1~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.163 ns" { clk alarm1~reg0 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.267 ns ( 43.87 % ) " "Info: Total cell delay = 1.267 ns ( 43.87 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.621 ns ( 56.13 % ) " "Info: Total interconnect delay = 1.621 ns ( 56.13 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.888 ns" { clk alarm1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.888 ns" { clk clk~out0 alarm1~reg0 } { 0.000ns 0.000ns 1.621ns } { 0.000ns 0.725ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.156 ns + " "Info: + Micro clock to output delay of source is 0.156 ns" {  } { { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.808 ns + Longest register pin " "Info: + Longest register to pin delay is 4.808 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alarm1~reg0 1 REG LC_X41_Y14_N0 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X41_Y14_N0; Fanout = 2; REG Node = 'alarm1~reg0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { alarm1~reg0 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 59 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.404 ns) + CELL(2.404 ns) 4.808 ns alarm1 2 PIN PIN_D8 0 " "Info: 2: + IC(2.404 ns) + CELL(2.404 ns) = 4.808 ns; Loc. = PIN_D8; Fanout = 0; PIN Node = 'alarm1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "4.808 ns" { alarm1~reg0 alarm1 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.404 ns ( 50.00 % ) " "Info: Total cell delay = 2.404 ns ( 50.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.404 ns ( 50.00 % ) " "Info: Total interconnect delay = 2.404 ns ( 50.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "4.808 ns" { alarm1~reg0 alarm1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.808 ns" { alarm1~reg0 alarm1 } { 0.000ns 2.404ns } { 0.000ns 2.404ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.888 ns" { clk alarm1~reg0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.888 ns" { clk clk~out0 alarm1~reg0 } { 0.000ns 0.000ns 1.621ns } { 0.000ns 0.725ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "4.808 ns" { alarm1~reg0 alarm1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "4.808 ns" { alarm1~reg0 alarm1 } { 0.000ns 2.404ns } { 0.000ns 2.404ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}
{ "Info" "ITDB_TH_RESULT" "en1 start tclk -1.913 ns register " "Info: th for register \"en1\" (data pin = \"start\", clock pin = \"tclk\") is -1.913 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "tclk destination 3.001 ns + Longest register " "Info: + Longest clock path from clock \"tclk\" to destination register is 3.001 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.828 ns) 0.828 ns tclk 1 CLK PIN_L3 15 " "Info: 1: + IC(0.000 ns) + CELL(0.828 ns) = 0.828 ns; Loc. = PIN_L3; Fanout = 15; CLK Node = 'tclk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { tclk } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 10 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.631 ns) + CELL(0.542 ns) 3.001 ns en1 2 REG LC_X41_Y14_N1 10 " "Info: 2: + IC(1.631 ns) + CELL(0.542 ns) = 3.001 ns; Loc. = LC_X41_Y14_N1; Fanout = 10; REG Node = 'en1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "2.173 ns" { tclk en1 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.370 ns ( 45.65 % ) " "Info: Total cell delay = 1.370 ns ( 45.65 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.631 ns ( 54.35 % ) " "Info: Total interconnect delay = 1.631 ns ( 54.35 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "3.001 ns" { tclk en1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.001 ns" { tclk tclk~out0 en1 } { 0.000ns 0.000ns 1.631ns } { 0.000ns 0.828ns 0.542ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" {  } { { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.014 ns - Shortest pin register " "Info: - Shortest pin to register delay is 5.014 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.725 ns) 0.725 ns start 1 PIN PIN_M1 94 " "Info: 1: + IC(0.000 ns) + CELL(0.725 ns) = 0.725 ns; Loc. = PIN_M1; Fanout = 94; PIN Node = 'start'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "" { start } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 11 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.066 ns) + CELL(0.223 ns) 5.014 ns en1 2 REG LC_X41_Y14_N1 10 " "Info: 2: + IC(4.066 ns) + CELL(0.223 ns) = 5.014 ns; Loc. = LC_X41_Y14_N1; Fanout = 10; REG Node = 'en1'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "4.289 ns" { start en1 } "NODE_NAME" } "" } } { "frequency.vhd" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/frequency/frequency.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.948 ns ( 18.91 % ) " "Info: Total cell delay = 0.948 ns ( 18.91 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.066 ns ( 81.09 % ) " "Info: Total interconnect delay = 4.066 ns ( 81.09 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "5.014 ns" { start en1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.014 ns" { start start~out0 en1 } { 0.000ns 0.000ns 4.066ns } { 0.000ns 0.725ns 0.223ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "3.001 ns" { tclk en1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "3.001 ns" { tclk tclk~out0 en1 } { 0.000ns 0.000ns 1.631ns } { 0.000ns 0.828ns 0.542ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "frequency" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/frequency/db/frequency.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/frequency/" "" "5.014 ns" { start en1 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.014 ns" { start start~out0 en1 } { 0.000ns 0.000ns 4.066ns } { 0.000ns 0.725ns 0.223ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}