fpga_project2.hier_info

此RS232通信协议用VHDL语言实现

|FPGA_Project2
CLK_REF => FRQCNT2:U2.TIMEBASE
CLK_REF => baud:U_baud.clk
JTAG_NEXUS_TCK => configurable_u3:U3.TCK
JTAG_NEXUS_TCK => FRQCNT2:U2.TCK
JTAG_NEXUS_TDI => FRQCNT2:U2.TDI
JTAG_NEXUS_TDO <= configurable_u3:U3.TDO
JTAG_NEXUS_TMS => configurable_u3:U3.TMS
JTAG_NEXUS_TMS => FRQCNT2:U2.TMS
LEDS[0] <= transfer_8_:U_transfer.txd_done
LEDS[1] <= <GND>
LEDS[2] <= <GND>
LEDS[3] <= <GND>
LEDS[4] <= <GND>
LEDS[5] <= <GND>
LEDS[6] <= <GND>
LEDS[7] <= <GND>
RS_CTS => ~NO_FANOUT~
RS_RTS <= <GND>
RS_RX => reciever_8_:U_reciever.rxdr
RS_TX <= transfer_8_:U_transfer.txd
TEST_BUTTON => reciever_8_:U_reciever.resetr
TEST_BUTTON => transfer_8_:U_transfer.resett
TEST_BUTTON => baud:U_baud.resetb


|FPGA_Project2|FRQCNT2:U2
FREQA => FREQA_i.IN0
FREQA => FRQCNT2_TOP:M_FC.FREQA
FREQB => FREQB_i.IN0
FREQB => FRQCNT2_TOP:M_FC.FREQB
TCK => TCK_i.IN0
TCK => FRQCNT2_TOP:M_FC.TCK
TDI => FRQCNT2_TOP:M_FC.TDI
TDO <= FRQCNT2_TOP:M_FC.tdo_iv_0
TDO_ENABLE <= FRQCNT2_TOP:M_FC.tdoenable
TIMEBASE => FRQCNT2_TOP:M_FC.TIMEBASE
TMS => FRQCNT2_TOP:M_FC.TMS
TRST => FRQCNT2_TOP:M_FC.TRST


|FPGA_Project2|FRQCNT2:U2|FRQCNT2_TOP:M_FC
FREQB => FRQCNT2_ENGINE_1:FR2.FREQB
FREQB_i => FRQCNT2_ENGINE_1:FR2.FREQB_i
FREQA => FRQCNT2_ENGINE:FR1.FREQA
FREQA_i => FRQCNT2_ENGINE:FR1.FREQA_i
TIMEBASE => FRQCNT2_DIVIDER:PD1.TIMEBASE
TIMEBASE => FRQCNT2_DIVIDER_1:PD2.TIMEBASE
TIMEBASE => FRQCNT2_ENGINE:FR1.TIMEBASE
TIMEBASE => FRQCNT2_ENGINE_1:FR2.TIMEBASE
TCK => FRQCNT2_TAPCONTROLLER:TAP1.TCK
TCK => FRQCNT2_DATAREG_INOUT_WRZ1:control_register.TCK
TCK => FRQCNT2_DATAREG_INOUT_WRZ0:user1_register.TCK
TCK => FRQCNT2_DATAREG_INOUT_WRZ0_1:user2_register.TCK
TCK => FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register.TCK
TMS => FRQCNT2_TAPCONTROLLER:TAP1.TMS
TRST => FRQCNT2_TAPCONTROLLER:TAP1.TRST
tdoenable <= FRQCNT2_TAPCONTROLLER:TAP1.tdoenable
TCK_i => FRQCNT2_TAPCONTROLLER:TAP1.TCK_i
tdo_iv_0 <= FRQCNT2_TAPCONTROLLER:TAP1.tdo_iv_0
TDI => G_546_a0_Z.DATAA
TDI => FRQCNT2_TAPCONTROLLER:TAP1.TDI
TDI => FRQCNT2_DATAREG_INOUT_WRZ1:control_register.TDI
TDI => FRQCNT2_DATAREG_INOUT_WRZ0:user1_register.TDI
TDI => FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register.TDI


|FPGA_Project2|FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1
sh_reg_0 => tdo_iv_0_and2_423_a_Z.DATAB
regout_0 => tdo_iv_0_and2_423_a_Z.DATAA
irout_1 <= irout_2_.REGOUT
irout_2 <= irout_3_.REGOUT
un1_ins_0_and2_2 <= ins_out_comb_proc_un1_ins_0_and2_2.COMBOUT
un16_tms_0_and2 <= tap_state_comb_proc_un16_tms_0_and2.COMBOUT
un11_ins_0_and2 <= ins_out_comb_proc_un11_ins_0_and2.COMBOUT
main_serialout_u_i_and6_3_420 => tdo_iv_0_and2_423_a_Z.DATAC
main_serialout_u_i_426 => tdo_iv_0_and2_423_Z.DATAD
main_serialout_u_i_and6_2 => tdo_iv_0_and2_423_Z.DATAC
tdo_iv_0 <= tdo_iv_0_0.COMBOUT
TCK_i => tdoenable_0.CLK
TCK_i => shiftir_r_Z.CLK
TCK_i => shiftdr_0.CLK
TCK_i => reset_r_Z.CLK
tdoenable <= tdoenable_0.REGOUT
un20_tapstate_r_0_and2 <= tap_out_comb_proc_un20_tapstate_r_0_and2.COMBOUT
shiftdr <= shiftdr_0.REGOUT
TDI => sh_ireg_3_.DATAA
TDI => byp_reg_Z.DATAA
TDI => FRQCNT2_DRNOOUT:id_reg_unit.TDI
TRST => tapstate_i_3_.ACLR
TRST => tapstate_i_2_.ACLR
TRST => tapstate_i_1_.ACLR
TRST => tapstate_i_0_.ACLR
TRST => tdoenable_0.ACLR
TRST => shiftir_r_Z.ACLR
TRST => shiftdr_0.ACLR
TRST => reset_r_Z.ACLR
TMS => tapstate_i_3_.DATAA
TMS => tapstate_i_2_.DATAA
TMS => tapstate_i_1_.DATAA
TMS => tapstate_i_0_.DATAA
TMS => tapstate_nxt_0_a_0_.DATAA
TCK => tapstate_i_3_.CLK
TCK => tapstate_i_2_.CLK
TCK => tapstate_i_1_.CLK
TCK => tapstate_i_0_.CLK
TCK => sh_ireg_3_.CLK
TCK => sh_ireg_2_.CLK
TCK => sh_ireg_1_.CLK
TCK => sh_ireg_0_.CLK
TCK => irout_3_.CLK
TCK => irout_2_.CLK
TCK => irout_1_.CLK
TCK => irout_i_0_.CLK
TCK => byp_reg_Z.CLK
TCK => FRQCNT2_DRNOOUT:id_reg_unit.TCK


|FPGA_Project2|FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|FRQCNT2_DRNOOUT:id_reg_unit
sh_reg_0 <= sh_reg_0_.REGOUT
un5_ins_0_and2 => sh_reg_31_.ENA
un5_ins_0_and2 => sh_reg_30_.ENA
un5_ins_0_and2 => sh_reg_29_.ENA
un5_ins_0_and2 => sh_reg_28_.ENA
un5_ins_0_and2 => sh_reg_27_.ENA
un5_ins_0_and2 => sh_reg_26_.ENA
un5_ins_0_and2 => sh_reg_25_.ENA
un5_ins_0_and2 => sh_reg_24_.ENA
un5_ins_0_and2 => sh_reg_23_.ENA
un5_ins_0_and2 => sh_reg_22_.ENA
un5_ins_0_and2 => sh_reg_21_.ENA
un5_ins_0_and2 => sh_reg_20_.ENA
un5_ins_0_and2 => sh_reg_19_.ENA
un5_ins_0_and2 => sh_reg_18_.ENA
un5_ins_0_and2 => sh_reg_17_.ENA
un5_ins_0_and2 => sh_reg_16_.ENA
un5_ins_0_and2 => sh_reg_15_.ENA
un5_ins_0_and2 => sh_reg_14_.ENA
un5_ins_0_and2 => sh_reg_13_.ENA
un5_ins_0_and2 => sh_reg_12_.ENA
un5_ins_0_and2 => sh_reg_11_.ENA
un5_ins_0_and2 => sh_reg_10_.ENA
un5_ins_0_and2 => sh_reg_9_.ENA
un5_ins_0_and2 => sh_reg_8_.ENA
un5_ins_0_and2 => sh_reg_7_.ENA
un5_ins_0_and2 => sh_reg_6_.ENA
un5_ins_0_and2 => sh_reg_5_.ENA
un5_ins_0_and2 => sh_reg_4_.ENA
un5_ins_0_and2 => sh_reg_3_.ENA
un5_ins_0_and2 => sh_reg_2_.ENA
un5_ins_0_and2 => sh_reg_1_.ENA
un5_ins_0_and2 => sh_reg_0_.ENA
shiftdr => sh_reg_31_.DATAB
shiftdr => sh_reg_30_.SCLR
shiftdr => sh_reg_29_.SCLR
shiftdr => sh_reg_28_.DATAA
shiftdr => sh_reg_27_.SCLR
shiftdr => sh_reg_26_.SCLR
shiftdr => sh_reg_25_.SCLR
shiftdr => sh_reg_24_.SCLR
shiftdr => sh_reg_23_.SCLR
shiftdr => sh_reg_22_.SCLR
shiftdr => sh_reg_21_.SCLR
shiftdr => sh_reg_20_.SCLR
shiftdr => sh_reg_19_.SCLR
shiftdr => sh_reg_18_.DATAA
shiftdr => sh_reg_17_.SCLR
shiftdr => sh_reg_16_.SCLR
shiftdr => sh_reg_15_.SCLR
shiftdr => sh_reg_14_.SCLR
shiftdr => sh_reg_13_.DATAA
shiftdr => sh_reg_12_.SCLR
shiftdr => sh_reg_11_.SCLR
shiftdr => sh_reg_10_.DATAA
shiftdr => sh_reg_9_.SCLR
shiftdr => sh_reg_8_.SCLR
shiftdr => sh_reg_7_.SCLR
shiftdr => sh_reg_6_.DATAA
shiftdr => sh_reg_5_.DATAA
shiftdr => sh_reg_4_.DATAA
shiftdr => sh_reg_3_.SCLR
shiftdr => sh_reg_2_.SCLR
shiftdr => sh_reg_1_.DATAA
shiftdr => sh_reg_0_.DATAA
TDI => sh_reg_31_.DATAA
TCK => sh_reg_31_.CLK
TCK => sh_reg_30_.CLK
TCK => sh_reg_29_.CLK
TCK => sh_reg_28_.CLK
TCK => sh_reg_27_.CLK
TCK => sh_reg_26_.CLK
TCK => sh_reg_25_.CLK
TCK => sh_reg_24_.CLK
TCK => sh_reg_23_.CLK
TCK => sh_reg_22_.CLK
TCK => sh_reg_21_.CLK
TCK => sh_reg_20_.CLK
TCK => sh_reg_19_.CLK
TCK => sh_reg_18_.CLK
TCK => sh_reg_17_.CLK
TCK => sh_reg_16_.CLK
TCK => sh_reg_15_.CLK
TCK => sh_reg_14_.CLK
TCK => sh_reg_13_.CLK
TCK => sh_reg_12_.CLK
TCK => sh_reg_11_.CLK
TCK => sh_reg_10_.CLK
TCK => sh_reg_9_.CLK
TCK => sh_reg_8_.CLK
TCK => sh_reg_7_.CLK
TCK => sh_reg_6_.CLK
TCK => sh_reg_5_.CLK
TCK => sh_reg_4_.CLK
TCK => sh_reg_3_.CLK
TCK => sh_reg_2_.CLK
TCK => sh_reg_1_.CLK
TCK => sh_reg_0_.CLK


|FPGA_Project2|FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_DIVIDER:PD1
regout_31 => count_31_.DATAC
regout_30 => count_30_.DATAC
regout_29 => count_29_.DATAC
regout_28 => count_28_.DATAC
regout_27 => count_27_.DATAC
regout_26 => count_26_.DATAC
regout_25 => count_25_.DATAC
regout_24 => count_24_.DATAC
regout_23 => count_23_.DATAC
regout_22 => count_22_.DATAC
regout_21 => count_21_.DATAC
regout_20 => count_20_.DATAC
regout_19 => count_19_.DATAC
regout_18 => count_18_.DATAC
regout_17 => count_17_.DATAC
regout_16 => count_16_.DATAC
regout_15 => count_15_.DATAC
regout_14 => count_14_.DATAC
regout_13 => count_13_.DATAC
regout_12 => count_12_.DATAC
regout_11 => count_11_.DATAC
regout_10 => count_10_.DATAC
regout_9 => count_9_.DATAC
regout_8 => count_8_.DATAC
regout_7 => count_7_.DATAC
regout_6 => count_6_.DATAC
regout_5 => count_5_.DATAC
regout_4 => count_4_.DATAC
regout_3 => count_3_.DATAC
regout_2 => count_2_.DATAC
regout_1 => count_1_.DATAC
regout_0 => count_0_.DATAC
ClockOut <= ClockOut_0.REGOUT
TIMEBASE => count_0_.CLK
TIMEBASE => count_1_.CLK
TIMEBASE => count_2_.CLK
TIMEBASE => count_3_.CLK
TIMEBASE => count_4_.CLK
TIMEBASE => count_5_.CLK
TIMEBASE => count_6_.CLK
TIMEBASE => count_7_.CLK
TIMEBASE => count_8_.CLK
TIMEBASE => count_9_.CLK
TIMEBASE => count_10_.CLK
TIMEBASE => count_11_.CLK
TIMEBASE => count_12_.CLK
TIMEBASE => count_13_.CLK
TIMEBASE => count_14_.CLK
TIMEBASE => count_15_.CLK
TIMEBASE => count_16_.CLK
TIMEBASE => count_17_.CLK
TIMEBASE => count_18_.CLK
TIMEBASE => count_19_.CLK
TIMEBASE => count_20_.CLK
TIMEBASE => count_21_.CLK
TIMEBASE => count_22_.CLK
TIMEBASE => count_23_.CLK
TIMEBASE => count_24_.CLK
TIMEBASE => count_25_.CLK
TIMEBASE => count_26_.CLK
TIMEBASE => count_27_.CLK
TIMEBASE => count_28_.CLK
TIMEBASE => count_29_.CLK
TIMEBASE => count_30_.CLK
TIMEBASE => count_31_.CLK
TIMEBASE => ClockOut_0.CLK


|FPGA_Project2|FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_DIVIDER_1:PD2
regout_31 => count_31_.DATAC
regout_30 => count_30_.DATAC
regout_29 => count_29_.DATAC
regout_28 => count_28_.DATAC
regout_27 => count_27_.DATAC
regout_26 => count_26_.DATAC
regout_25 => count_25_.DATAC
regout_24 => count_24_.DATAC
regout_23 => count_23_.DATAC
regout_22 => count_22_.DATAC
regout_21 => count_21_.DATAC
regout_20 => count_20_.DATAC
regout_19 => count_19_.DATAC
regout_18 => count_18_.DATAC
regout_17 => count_17_.DATAC
regout_16 => count_16_.DATAC
regout_15 => count_15_.DATAC
regout_14 => count_14_.DATAC
regout_13 => count_13_.DATAC
regout_12 => count_12_.DATAC
regout_11 => count_11_.DATAC
regout_10 => count_10_.DATAC
regout_9 => count_9_.DATAC
regout_8 => count_8_.DATAC
regout_7 => count_7_.DATAC
regout_6 => count_6_.DATAC
regout_5 => count_5_.DATAC
regout_4 => count_4_.DATAC
regout_3 => count_3_.DATAC
regout_2 => count_2_.DATAC
regout_1 => count_1_.DATAC
regout_0 => count_0_.DATAC
ClockOut <= ClockOut_0.REGOUT
TIMEBASE => count_0_.CLK
TIMEBASE => count_1_.CLK
TIMEBASE => count_2_.CLK
TIMEBASE => count_3_.CLK
TIMEBASE => count_4_.CLK
TIMEBASE => count_5_.CLK
TIMEBASE => count_6_.CLK
TIMEBASE => count_7_.CLK
TIMEBASE => count_8_.CLK
TIMEBASE => count_9_.CLK
TIMEBASE => count_10_.CLK
TIMEBASE => count_11_.CLK
TIMEBASE => count_12_.CLK
TIMEBASE => count_13_.CLK
TIMEBASE => count_14_.CLK
TIMEBASE => count_15_.CLK
TIMEBASE => count_16_.CLK
TIMEBASE => count_17_.CLK
TIMEBASE => count_18_.CLK
TIMEBASE => count_19_.CLK
TIMEBASE => count_20_.CLK
TIMEBASE => count_21_.CLK
TIMEBASE => count_22_.CLK
TIMEBASE => count_23_.CLK
TIMEBASE => count_24_.CLK
TIMEBASE => count_25_.CLK
TIMEBASE => count_26_.CLK
TIMEBASE => count_27_.CLK
TIMEBASE => count_28_.CLK
TIMEBASE => count_29_.CLK
TIMEBASE => count_30_.CLK
TIMEBASE => count_31_.CLK
TIMEBASE => ClockOut_0.CLK


|FPGA_Project2|FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_ENGINE:FR1
latchedcount_f_0 <= latchedcount_f_0_.REGOUT
latchedcount_f_1 <= latchedcount_f_1_.REGOUT
latchedcount_f_2 <= latchedcount_f_2_.REGOUT
latchedcount_f_3 <= latchedcount_f_3_.REGOUT
latchedcount_f_4 <= latchedcount_f_4_.REGOUT
latchedcount_f_5 <= latchedcount_f_5_.REGOUT
latchedcount_f_6 <= latchedcount_f_6_.REGOUT
latchedcount_f_7 <= latchedcount_f_7_.REGOUT
latchedcount_f_8 <= latchedcount_f_8_.REGOUT
latchedcount_f_9 <= latchedcount_f_9_.REGOUT
latchedcount_f_10 <= latchedcount_f_10_.REGOUT
latchedcount_f_11 <= latchedcount_f_11_.REGOUT
latchedcount_f_12 <= latchedcount_f_12_.REGOUT
latchedcount_f_13 <= latchedcount_f_13_.REGOUT
latchedcount_f_14 <= latchedcount_f_14_.REGOUT
latchedcount_f_15 <= latchedcount_f_15_.REGOUT
latchedcount_f_16 <= latchedcount_f_16_.REGOUT
latchedcount_f_17 <= latchedcount_f_17_.REGOUT
latchedcount_f_18 <= latchedcount_f_18_.REGOUT
latchedcount_f_19 <= latchedcount_f_19_.REGOUT
latchedcount_f_20 <= latchedcount_f_20_.REGOUT
latchedcount_f_21 <= latchedcount_f_21_.REGOUT
latchedcount_f_22 <= latchedcount_f_22_.REGOUT
latchedcount_f_23 <= latchedcount_f_23_.REGOUT
latchedcount_f_24 <= latchedcount_f_24_.REGOUT
latchedcount_f_25 <= latchedcount_f_25_.REGOUT
latchedcount_f_26 <= latchedcount_f_26_.REGOUT
latchedcount_f_27 <= latchedcount_f_27_.REGOUT
latchedcount_f_28 <= latchedcount_f_28_.REGOUT
latchedcount_f_29 <= latchedcount_f_29_.REGOUT
latchedcount_f_30 <= latchedcount_f_30_.REGOUT
sh_reg_30 => latchedcount_r_30_.DATAB
sh_reg_29 => latchedcount_r_29_.DATAB
sh_reg_28 => latchedcount_r_28_.DATAB
sh_reg_27 => latchedcount_r_27_.DATAB
sh_reg_26 => latchedcount_r_26_.DATAB
sh_reg_25 => latchedcount_r_25_.DATAB
sh_reg_24 => latchedcount_r_24_.DATAB
sh_reg_23 => latchedcount_r_23_.DATAB
sh_reg_22 => latchedcount_r_22_.DATAB
sh_reg_21 => latchedcount_r_21_.DATAB
sh_reg_20 => latchedcount_r_20_.DATAB
sh_reg_19 => latchedcount_r_19_.DATAB
sh_reg_18 => latchedcount_r_18_.DATAB
sh_reg_17 => latchedcount_r_17_.DATAB
sh_reg_16 => latchedcount_r_16_.DATAB
sh_reg_15 => latchedcount_r_15_.DATAB
sh_reg_14 => latchedcount_r_14_.DATAB
sh_reg_13 => latchedcount_r_13_.DATAB
sh_reg_12 => latchedcount_r_12_.DATAB
sh_reg_11 => latchedcount_r_11_.DATAB
sh_reg_10 => latchedcount_r_10_.DATAB
sh_reg_9 => latchedcount_r_9_.DATAB