fpga_project2.tan.qmsg

此RS232通信协议用VHDL语言实现

{ "Warning" "WTAN_CLOCK_WILL_NOT_OPERATE" "CLK_REF 8 " "Warning: Circuit may not operate. Detected 8 non-operational path(s) clocked by clock \"CLK_REF\" with clock skew larger than data delay. See Compilation Report for details." {  } {  } 0 0 "Circuit may not operate. Detected %2!d! non-operational path(s) clocked by clock \"%1!s!\" with clock skew larger than data delay. See Compilation Report for details." 0 0}
{ "Info" "ITDB_FULL_NEGATIVE_HOLD_RESULT" "reciever_8_:U_reciever\|INST_rbuf_0 transfer_8_:U_transfer\|txdbuf_temp_0 CLK_REF 4.09 ns " "Info: Found hold time violation between source  pin or register \"reciever_8_:U_reciever\|INST_rbuf_0\" and destination pin or register \"transfer_8_:U_transfer\|txdbuf_temp_0\" for clock \"CLK_REF\" (Hold time is 4.09 ns)" { { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "4.931 ns + Largest " "Info: + Largest clock skew is 4.931 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_REF destination 10.871 ns + Longest register " "Info: + Longest clock path from clock \"CLK_REF\" to destination register is 10.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK_REF 1 CLK PIN_152 189 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_152; Fanout = 189; CLK Node = 'CLK_REF'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { CLK_REF } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8305 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.790 ns) + CELL(0.720 ns) 2.640 ns baud:U_baud\|INST_bclk 2 REG LC_X8_Y13_N4 165 " "Info: 2: + IC(0.790 ns) + CELL(0.720 ns) = 2.640 ns; Loc. = LC_X8_Y13_N4; Fanout = 165; REG Node = 'baud:U_baud\|INST_bclk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "1.510 ns" { CLK_REF baud:U_baud|INST_bclk } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4528 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.745 ns) + CELL(0.720 ns) 6.105 ns reciever_8_:U_reciever\|INST_r_ready 3 REG LC_X23_Y10_N5 12 " "Info: 3: + IC(2.745 ns) + CELL(0.720 ns) = 6.105 ns; Loc. = LC_X23_Y10_N5; Fanout = 12; REG Node = 'reciever_8_:U_reciever\|INST_r_ready'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "3.465 ns" { baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5571 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.219 ns) + CELL(0.547 ns) 10.871 ns transfer_8_:U_transfer\|txdbuf_temp_0 4 REG LC_X30_Y16_N4 1 " "Info: 4: + IC(4.219 ns) + CELL(0.547 ns) = 10.871 ns; Loc. = LC_X30_Y16_N4; Fanout = 1; REG Node = 'transfer_8_:U_transfer\|txdbuf_temp_0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "4.766 ns" { reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 929 24 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.117 ns ( 28.67 % ) " "Info: Total cell delay = 3.117 ns ( 28.67 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.754 ns ( 71.33 % ) " "Info: Total interconnect delay = 7.754 ns ( 71.33 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "10.871 ns" { CLK_REF baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.871 ns" { CLK_REF CLK_REF~out0 baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } { 0.000ns 0.000ns 0.790ns 2.745ns 4.219ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_REF source 5.940 ns - Shortest register " "Info: - Shortest clock path from clock \"CLK_REF\" to source register is 5.940 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK_REF 1 CLK PIN_152 189 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_152; Fanout = 189; CLK Node = 'CLK_REF'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { CLK_REF } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8305 12 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.790 ns) + CELL(0.720 ns) 2.640 ns baud:U_baud\|INST_bclk 2 REG LC_X8_Y13_N4 165 " "Info: 2: + IC(0.790 ns) + CELL(0.720 ns) = 2.640 ns; Loc. = LC_X8_Y13_N4; Fanout = 165; REG Node = 'baud:U_baud\|INST_bclk'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "1.510 ns" { CLK_REF baud:U_baud|INST_bclk } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4528 16 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.753 ns) + CELL(0.547 ns) 5.940 ns reciever_8_:U_reciever\|INST_rbuf_0 3 REG LC_X29_Y16_N5 2 " "Info: 3: + IC(2.753 ns) + CELL(0.547 ns) = 5.940 ns; Loc. = LC_X29_Y16_N5; Fanout = 2; REG Node = 'reciever_8_:U_reciever\|INST_rbuf_0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "3.300 ns" { baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_rbuf_0 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5577 24 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 40.35 % ) " "Info: Total cell delay = 2.397 ns ( 40.35 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.543 ns ( 59.65 % ) " "Info: Total interconnect delay = 3.543 ns ( 59.65 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "5.940 ns" { CLK_REF baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_rbuf_0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.940 ns" { CLK_REF CLK_REF~out0 baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_rbuf_0 } { 0.000ns 0.000ns 0.790ns 2.753ns } { 0.000ns 1.130ns 0.720ns 0.547ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "10.871 ns" { CLK_REF baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.871 ns" { CLK_REF CLK_REF~out0 baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } { 0.000ns 0.000ns 0.790ns 2.745ns 4.219ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "5.940 ns" { CLK_REF baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_rbuf_0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.940 ns" { CLK_REF CLK_REF~out0 baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_rbuf_0 } { 0.000ns 0.000ns 0.790ns 2.753ns } { 0.000ns 1.130ns 0.720ns 0.547ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns - " "Info: - Micro clock to output delay of source is 0.173 ns" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5577 24 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.680 ns - Shortest register register " "Info: - Shortest register to register delay is 0.680 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reciever_8_:U_reciever\|INST_rbuf_0 1 REG LC_X29_Y16_N5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X29_Y16_N5; Fanout = 2; REG Node = 'reciever_8_:U_reciever\|INST_rbuf_0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { reciever_8_:U_reciever|INST_rbuf_0 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5577 24 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.591 ns) + CELL(0.089 ns) 0.680 ns transfer_8_:U_transfer\|txdbuf_temp_0 2 REG LC_X30_Y16_N4 1 " "Info: 2: + IC(0.591 ns) + CELL(0.089 ns) = 0.680 ns; Loc. = LC_X30_Y16_N4; Fanout = 1; REG Node = 'transfer_8_:U_transfer\|txdbuf_temp_0'" {  } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "0.680 ns" { reciever_8_:U_reciever|INST_rbuf_0 transfer_8_:U_transfer|txdbuf_temp_