📄 fpga_project2.tan.qmsg
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{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "reciever_8_:U_reciever\|INST_r_ready " "Info: Detected ripple clock \"reciever_8_:U_reciever\|INST_r_ready\" as buffer" { } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5571 16 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "reciever_8_:U_reciever\|INST_r_ready" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "baud:U_baud\|INST_bclk " "Info: Detected ripple clock \"baud:U_baud\|INST_bclk\" as buffer" { } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4528 16 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "baud:U_baud\|INST_bclk" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "JTAG_NEXUS_TCK register FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|irout\[1\] register configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length\|sh_reg_15 104.18 MHz 9.599 ns Internal " "Info: Clock \"JTAG_NEXUS_TCK\" has Internal fmax of 104.18 MHz between source register \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|irout\[1\]\" and destination register \"configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length\|sh_reg_15\" (period= 9.599 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.351 ns + Longest register register " "Info: + Longest register to register delay is 9.351 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|irout\[1\] 1 REG LC_X23_Y18_N3 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y18_N3; Fanout = 6; REG Node = 'FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|irout\[1\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] } "NODE_NAME" } "" } } { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 528 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.888 ns) + CELL(0.088 ns) 1.976 ns FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|un11_ins_0_and2 2 COMB LC_X23_Y18_N9 8 " "Info: 2: + IC(1.888 ns) + CELL(0.088 ns) = 1.976 ns; Loc. = LC_X23_Y18_N9; Fanout = 8; COMB Node = 'FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|un11_ins_0_and2'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "1.976 ns" { FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|un11_ins_0_and2 } "NODE_NAME" } "" } } { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 493 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.871 ns) + CELL(0.340 ns) 3.187 ns FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|tdo_iv_0_and2_423_a 3 COMB LC_X23_Y18_N7 1 " "Info: 3: + IC(0.871 ns) + CELL(0.340 ns) = 3.187 ns; Loc. = LC_X23_Y18_N7; Fanout = 1; COMB Node = 'FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|tdo_iv_0_and2_423_a'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "1.211 ns" { FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|un11_ins_0_and2 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423_a } "NODE_NAME" } "" } } { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 539 27 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.942 ns) + CELL(0.340 ns) 4.469 ns FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|tdo_iv_0_and2_423 4 COMB LC_X22_Y14_N2 1 " "Info: 4: + IC(0.942 ns) + CELL(0.340 ns) = 4.469 ns; Loc. = LC_X22_Y14_N2; Fanout = 1; COMB Node = 'FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|tdo_iv_0_and2_423'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "1.282 ns" { FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423_a FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423 } "NODE_NAME" } "" } } { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 538 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.330 ns) + CELL(0.454 ns) 5.253 ns FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|tdo_iv_0 5 COMB LC_X22_Y14_N7 6 " "Info: 5: + IC(0.330 ns) + CELL(0.454 ns) = 5.253 ns; Loc. = LC_X22_Y14_N7; Fanout = 6; COMB Node = 'FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|tdo_iv_0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "0.784 ns" { FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0 } "NODE_NAME" } "" } } { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 497 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.435 ns) + CELL(0.225 ns) 7.913 ns configurable_u3:U3\|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1\|byp_reg_in 6 COMB LC_X37_Y17_N9 3 " "Info: 6: + IC(2.435 ns) + CELL(0.225 ns) = 7.913 ns; Loc. = LC_X37_Y17_N9; Fanout = 3; COMB Node = 'configurable_u3:U3\|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1\|byp_reg_in'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "2.660 ns" { FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0 configurable_u3:U3|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1|byp_reg_in } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7214 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.200 ns) + CELL(0.238 ns) 9.351 ns configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length\|sh_reg_15 7 REG LC_X38_Y16_N1 1 " "Info: 7: + IC(1.200 ns) + CELL(0.238 ns) = 9.351 ns; Loc. = LC_X38_Y16_N1; Fanout = 1; REG Node = 'configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length\|sh_reg_15'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "1.438 ns" { configurable_u3:U3|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1|byp_reg_in configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 3665 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.685 ns ( 18.02 % ) " "Info: Total cell delay = 1.685 ns ( 18.02 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.666 ns ( 81.98 % ) " "Info: Total interconnect delay = 7.666 ns ( 81.98 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "9.351 ns" { FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|un11_ins_0_and2 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423_a FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0 configurable_u3:U3|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1|byp_reg_in configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.351 ns" { FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|un11_ins_0_and2 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423_a FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0 configurable_u3:U3|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1|byp_reg_in configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } { 0.000ns 1.888ns 0.871ns 0.942ns 0.330ns 2.435ns 1.200ns } { 0.000ns 0.088ns 0.340ns 0.340ns 0.454ns 0.225ns 0.238ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.046 ns - Smallest " "Info: - Smallest clock skew is -0.046 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "JTAG_NEXUS_TCK destination 6.027 ns + Shortest register " "Info: + Shortest clock path from clock \"JTAG_NEXUS_TCK\" to destination register is 6.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns JTAG_NEXUS_TCK 1 CLK PIN_7 314 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_7; Fanout = 314; CLK Node = 'JTAG_NEXUS_TCK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { JTAG_NEXUS_TCK } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8306 12 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.350 ns) + CELL(0.547 ns) 6.027 ns configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length\|sh_reg_15 2 REG LC_X38_Y16_N1 1 " "Info: 2: + IC(4.350 ns) + CELL(0.547 ns) = 6.027 ns; Loc. = LC_X38_Y16_N1; Fanout = 1; REG Node = 'configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length\|sh_reg_15'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "4.897 ns" { JTAG_NEXUS_TCK configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 3665 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 27.82 % ) " "Info: Total cell delay = 1.677 ns ( 27.82 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.350 ns ( 72.18 % ) " "Info: Total interconnect delay = 4.350 ns ( 72.18 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "6.027 ns" { JTAG_NEXUS_TCK configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.027 ns" { JTAG_NEXUS_TCK JTAG_NEXUS_TCK~out0 configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } { 0.000ns 0.000ns 4.350ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "JTAG_NEXUS_TCK source 6.073 ns - Longest register " "Info: - Longest clock path from clock \"JTAG_NEXUS_TCK\" to source register is 6.073 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns JTAG_NEXUS_TCK 1 CLK PIN_7 314 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_7; Fanout = 314; CLK Node = 'JTAG_NEXUS_TCK'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { JTAG_NEXUS_TCK } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8306 12 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.396 ns) + CELL(0.547 ns) 6.073 ns FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|irout\[1\] 2 REG LC_X23_Y18_N3 6 " "Info: 2: + IC(4.396 ns) + CELL(0.547 ns) = 6.073 ns; Loc. = LC_X23_Y18_N3; Fanout = 6; REG Node = 'FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|irout\[1\]'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "4.943 ns" { JTAG_NEXUS_TCK FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] } "NODE_NAME" } "" } } { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 528 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.677 ns ( 27.61 % ) " "Info: Total cell delay = 1.677 ns ( 27.61 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.396 ns ( 72.39 % ) " "Info: Total interconnect delay = 4.396 ns ( 72.39 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "6.073 ns" { JTAG_NEXUS_TCK FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.073 ns" { JTAG_NEXUS_TCK JTAG_NEXUS_TCK~out0 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] } { 0.000ns 0.000ns 4.396ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "6.027 ns" { JTAG_NEXUS_TCK configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.027 ns" { JTAG_NEXUS_TCK JTAG_NEXUS_TCK~out0 configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } { 0.000ns 0.000ns 4.350ns } { 0.000ns 1.130ns 0.547ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "6.073 ns" { JTAG_NEXUS_TCK FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.073 ns" { JTAG_NEXUS_TCK JTAG_NEXUS_TCK~out0 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] } { 0.000ns 0.000ns 4.396ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 528 18 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 3665 24 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "9.351 ns" { FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|un11_ins_0_and2 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423_a FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0 configurable_u3:U3|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1|byp_reg_in configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "9.351 ns" { FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|un11_ins_0_and2 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423_a FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0_and2_423 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|tdo_iv_0 configurable_u3:U3|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1|byp_reg_in configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } { 0.000ns 1.888ns 0.871ns 0.942ns 0.330ns 2.435ns 1.200ns } { 0.000ns 0.088ns 0.340ns 0.340ns 0.454ns 0.225ns 0.238ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "6.027 ns" { JTAG_NEXUS_TCK configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.027 ns" { JTAG_NEXUS_TCK JTAG_NEXUS_TCK~out0 configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterOutput_Length|sh_reg_15 } { 0.000ns 0.000ns 4.350ns } { 0.000ns 1.130ns 0.547ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "6.073 ns" { JTAG_NEXUS_TCK FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "6.073 ns" { JTAG_NEXUS_TCK JTAG_NEXUS_TCK~out0 FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|irout[1] } { 0.000ns 0.000ns 4.396ns } { 0.000ns 1.130ns 0.547ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "CLK_REF register transfer_8_:U_transfer\|txdbuf_temp_0 register transfer_8_:U_transfer\|INST_txd 61.65 MHz 16.22 ns Internal " "Info: Clock \"CLK_REF\" has Internal fmax of 61.65 MHz between source register \"transfer_8_:U_transfer\|txdbuf_temp_0\" and destination register \"transfer_8_:U_transfer\|INST_txd\" (period= 16.22 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.977 ns + Longest register register " "Info: + Longest register to register delay is 2.977 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns transfer_8_:U_transfer\|txdbuf_temp_0 1 REG LC_X30_Y16_N4 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X30_Y16_N4; Fanout = 1; REG Node = 'transfer_8_:U_transfer\|txdbuf_temp_0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { transfer_8_:U_transfer|txdbuf_temp_0 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 929 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.396 ns) + CELL(0.340 ns) 0.736 ns transfer_8_:U_transfer\|n6s~18 2 COMB LC_X30_Y16_N8 1 " "Info: 2: + IC(0.396 ns) + CELL(0.340 ns) = 0.736 ns; Loc. = LC_X30_Y16_N8; Fanout = 1; COMB Node = 'transfer_8_:U_transfer\|n6s~18'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "0.736 ns" { transfer_8_:U_transfer|txdbuf_temp_0 transfer_8_:U_transfer|n6s~18 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 783 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.317 ns) + CELL(0.340 ns) 1.393 ns transfer_8_:U_transfer\|n6s~19 3 COMB LC_X30_Y16_N6 1 " "Info: 3: + IC(0.317 ns) + CELL(0.340 ns) = 1.393 ns; Loc. = LC_X30_Y16_N6; Fanout = 1; COMB Node = 'transfer_8_:U_transfer\|n6s~19'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "0.657 ns" { transfer_8_:U_transfer|n6s~18 transfer_8_:U_transfer|n6s~19 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 783 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.345 ns) + CELL(0.454 ns) 2.192 ns transfer_8_:U_transfer\|txd_in~273 4 COMB LC_X30_Y16_N3 1 " "Info: 4: + IC(0.345 ns) + CELL(0.454 ns) = 2.192 ns; Loc. = LC_X30_Y16_N3; Fanout = 1; COMB Node = 'transfer_8_:U_transfer\|txd_in~273'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "0.799 ns" { transfer_8_:U_transfer|n6s~19 transfer_8_:U_transfer|txd_in~273 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 768 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.318 ns) + CELL(0.467 ns) 2.977 ns transfer_8_:U_transfer\|INST_txd 5 REG LC_X30_Y16_N7 2 " "Info: 5: + IC(0.318 ns) + CELL(0.467 ns) = 2.977 ns; Loc. = LC_X30_Y16_N7; Fanout = 2; REG Node = 'transfer_8_:U_transfer\|INST_txd'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "0.785 ns" { transfer_8_:U_transfer|txd_in~273 transfer_8_:U_transfer|INST_txd } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1021 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.601 ns ( 53.78 % ) " "Info: Total cell delay = 1.601 ns ( 53.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.376 ns ( 46.22 % ) " "Info: Total interconnect delay = 1.376 ns ( 46.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "2.977 ns" { transfer_8_:U_transfer|txdbuf_temp_0 transfer_8_:U_transfer|n6s~18 transfer_8_:U_transfer|n6s~19 transfer_8_:U_transfer|txd_in~273 transfer_8_:U_transfer|INST_txd } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.977 ns" { transfer_8_:U_transfer|txdbuf_temp_0 transfer_8_:U_transfer|n6s~18 transfer_8_:U_transfer|n6s~19 transfer_8_:U_transfer|txd_in~273 transfer_8_:U_transfer|INST_txd } { 0.000ns 0.396ns 0.317ns 0.345ns 0.318ns } { 0.000ns 0.340ns 0.340ns 0.454ns 0.467ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.931 ns - Smallest " "Info: - Smallest clock skew is -4.931 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_REF destination 5.940 ns + Shortest register " "Info: + Shortest clock path from clock \"CLK_REF\" to destination register is 5.940 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK_REF 1 CLK PIN_152 189 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_152; Fanout = 189; CLK Node = 'CLK_REF'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { CLK_REF } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8305 12 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.790 ns) + CELL(0.720 ns) 2.640 ns baud:U_baud\|INST_bclk 2 REG LC_X8_Y13_N4 165 " "Info: 2: + IC(0.790 ns) + CELL(0.720 ns) = 2.640 ns; Loc. = LC_X8_Y13_N4; Fanout = 165; REG Node = 'baud:U_baud\|INST_bclk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "1.510 ns" { CLK_REF baud:U_baud|INST_bclk } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4528 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.753 ns) + CELL(0.547 ns) 5.940 ns transfer_8_:U_transfer\|INST_txd 3 REG LC_X30_Y16_N7 2 " "Info: 3: + IC(2.753 ns) + CELL(0.547 ns) = 5.940 ns; Loc. = LC_X30_Y16_N7; Fanout = 2; REG Node = 'transfer_8_:U_transfer\|INST_txd'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "3.300 ns" { baud:U_baud|INST_bclk transfer_8_:U_transfer|INST_txd } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1021 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.397 ns ( 40.35 % ) " "Info: Total cell delay = 2.397 ns ( 40.35 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.543 ns ( 59.65 % ) " "Info: Total interconnect delay = 3.543 ns ( 59.65 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "5.940 ns" { CLK_REF baud:U_baud|INST_bclk transfer_8_:U_transfer|INST_txd } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.940 ns" { CLK_REF CLK_REF~out0 baud:U_baud|INST_bclk transfer_8_:U_transfer|INST_txd } { 0.000ns 0.000ns 0.790ns 2.753ns } { 0.000ns 1.130ns 0.720ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_REF source 10.871 ns - Longest register " "Info: - Longest clock path from clock \"CLK_REF\" to source register is 10.871 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.130 ns) 1.130 ns CLK_REF 1 CLK PIN_152 189 " "Info: 1: + IC(0.000 ns) + CELL(1.130 ns) = 1.130 ns; Loc. = PIN_152; Fanout = 189; CLK Node = 'CLK_REF'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { CLK_REF } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8305 12 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.790 ns) + CELL(0.720 ns) 2.640 ns baud:U_baud\|INST_bclk 2 REG LC_X8_Y13_N4 165 " "Info: 2: + IC(0.790 ns) + CELL(0.720 ns) = 2.640 ns; Loc. = LC_X8_Y13_N4; Fanout = 165; REG Node = 'baud:U_baud\|INST_bclk'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "1.510 ns" { CLK_REF baud:U_baud|INST_bclk } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4528 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.745 ns) + CELL(0.720 ns) 6.105 ns reciever_8_:U_reciever\|INST_r_ready 3 REG LC_X23_Y10_N5 12 " "Info: 3: + IC(2.745 ns) + CELL(0.720 ns) = 6.105 ns; Loc. = LC_X23_Y10_N5; Fanout = 12; REG Node = 'reciever_8_:U_reciever\|INST_r_ready'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "3.465 ns" { baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5571 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.219 ns) + CELL(0.547 ns) 10.871 ns transfer_8_:U_transfer\|txdbuf_temp_0 4 REG LC_X30_Y16_N4 1 " "Info: 4: + IC(4.219 ns) + CELL(0.547 ns) = 10.871 ns; Loc. = LC_X30_Y16_N4; Fanout = 1; REG Node = 'transfer_8_:U_transfer\|txdbuf_temp_0'" { } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "4.766 ns" { reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } "NODE_NAME" } "" } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 929 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.117 ns ( 28.67 % ) " "Info: Total cell delay = 3.117 ns ( 28.67 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.754 ns ( 71.33 % ) " "Info: Total interconnect delay = 7.754 ns ( 71.33 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "10.871 ns" { CLK_REF baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.871 ns" { CLK_REF CLK_REF~out0 baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } { 0.000ns 0.000ns 0.790ns 2.745ns 4.219ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "5.940 ns" { CLK_REF baud:U_baud|INST_bclk transfer_8_:U_transfer|INST_txd } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.940 ns" { CLK_REF CLK_REF~out0 baud:U_baud|INST_bclk transfer_8_:U_transfer|INST_txd } { 0.000ns 0.000ns 0.790ns 2.753ns } { 0.000ns 1.130ns 0.720ns 0.547ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "10.871 ns" { CLK_REF baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.871 ns" { CLK_REF CLK_REF~out0 baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } { 0.000ns 0.000ns 0.790ns 2.745ns 4.219ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.173 ns + " "Info: + Micro clock to output delay of source is 0.173 ns" { } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 929 24 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.029 ns + " "Info: + Micro setup delay of destination is 0.029 ns" { } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1021 16 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 929 24 0 } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1021 16 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "2.977 ns" { transfer_8_:U_transfer|txdbuf_temp_0 transfer_8_:U_transfer|n6s~18 transfer_8_:U_transfer|n6s~19 transfer_8_:U_transfer|txd_in~273 transfer_8_:U_transfer|INST_txd } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "2.977 ns" { transfer_8_:U_transfer|txdbuf_temp_0 transfer_8_:U_transfer|n6s~18 transfer_8_:U_transfer|n6s~19 transfer_8_:U_transfer|txd_in~273 transfer_8_:U_transfer|INST_txd } { 0.000ns 0.396ns 0.317ns 0.345ns 0.318ns } { 0.000ns 0.340ns 0.340ns 0.454ns 0.467ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "5.940 ns" { CLK_REF baud:U_baud|INST_bclk transfer_8_:U_transfer|INST_txd } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "5.940 ns" { CLK_REF CLK_REF~out0 baud:U_baud|INST_bclk transfer_8_:U_transfer|INST_txd } { 0.000ns 0.000ns 0.790ns 2.753ns } { 0.000ns 1.130ns 0.720ns 0.547ns } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "10.871 ns" { CLK_REF baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } "NODE_NAME" } "" } } { "d:/altera/quartus51/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus51/bin/Technology_Viewer.qrui" "10.871 ns" { CLK_REF CLK_REF~out0 baud:U_baud|INST_bclk reciever_8_:U_reciever|INST_r_ready transfer_8_:U_transfer|txdbuf_temp_0 } { 0.000ns 0.000ns 0.790ns 2.745ns 4.219ns } { 0.000ns 1.130ns 0.720ns 0.720ns 0.547ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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