fpga_project2.map.qmsg

此RS232通信协议用VHDL语言实现

{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_11 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_11\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4500 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_10 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_10\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4502 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_9 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_9\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4504 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_8 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_8\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4506 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "transfer_8_:U_transfer\|pro1_xcnt16_4 data_in GND " "Warning: Reduced register \"transfer_8_:U_transfer\|pro1_xcnt16_4\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1007 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_30 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_30\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4526 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_29 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_29\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4464 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_28 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_28\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4466 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_27 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_27\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4468 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_26 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_26\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4470 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_25 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_25\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4472 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_24 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_24\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4474 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_23 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_23\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4476 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_22 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_22\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4478 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_21 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_21\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4480 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_20 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_20\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4482 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "LEDS\[1\] GND " "Warning: Pin \"LEDS\[1\]\" stuck at GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDS\[2\] GND " "Warning: Pin \"LEDS\[2\]\" stuck at GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDS\[3\] GND " "Warning: Pin \"LEDS\[3\]\" stuck at GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDS\[4\] GND " "Warning: Pin \"LEDS\[4\]\" stuck at GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDS\[5\] GND " "Warning: Pin \"LEDS\[5\]\" stuck at GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDS\[6\] GND " "Warning: Pin \"LEDS\[6\]\" stuck at GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "LEDS\[7\] GND " "Warning: Pin \"LEDS\[7\]\" stuck at GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8313 27 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0} { "Warning" "WOPT_MLS_STUCK_PIN" "RS_RTS GND " "Warning: Pin \"RS_RTS\" stuck at GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8314 12 0 } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7282 24 0 } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1021 16 0 } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1019 16 0 } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4528 16 0 } } { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5611 16 0 } }  } 0 0 "Registers with preset signals will power-up high" 0 0}
{ "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN_HDR" "1 " "Warning: Design contains 1 input pin(s) that do not drive logic" { { "Warning" "WSCL_SCL_UNNECESSARY_INPUT_PIN" "RS_CTS " "Warning: No output dependent on input pin \"RS_CTS\"" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8309 12 0 } }  } 0 0 "No output dependent on input pin \"%1!s!\"" 0 0}  } {  } 0 0 "Design contains %1!d! input pin(s) that do not drive logic" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "909 " "Info: Implemented 909 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "7 " "Info: Implemented 7 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "11 " "Info: Implemented 11 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "891 " "Info: Implemented 891 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 47 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 47 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 30 13:50:04 2008 " "Info: Processing ended: Wed Jul 30 13:50:04 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:19 " "Info: Elapsed time: 00:00:19" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}