fpga_project2.map.qmsg

此RS232通信协议用VHDL语言实现

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_COMPARE baud:U_baud\|LPM_COMPARE:LPM_COMPARE_32_32_1 " "Info: Elaborating entity \"LPM_COMPARE\" for hierarchy \"baud:U_baud\|LPM_COMPARE:LPM_COMPARE_32_32_1\"" {  } { { "FPGA_Project2.edn" "LPM_COMPARE_32_32_1" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4685 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_rhd.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/cmpr_rhd.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_rhd " "Info: Found entity 1: cmpr_rhd" {  } { { "db/cmpr_rhd.tdf" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/cmpr_rhd.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_rhd baud:U_baud\|LPM_COMPARE:LPM_COMPARE_32_32_1\|cmpr_rhd:auto_generated " "Info: Elaborating entity \"cmpr_rhd\" for hierarchy \"baud:U_baud\|LPM_COMPARE:LPM_COMPARE_32_32_1\|cmpr_rhd:auto_generated\"" {  } { { "LPM_COMPARE.tdf" "auto_generated" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_COMPARE.tdf" 278 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "reciever_8_ reciever_8_:U_reciever " "Info: Elaborating entity \"reciever_8_\" for hierarchy \"reciever_8_:U_reciever\"" {  } { { "FPGA_Project2.edn" "U_reciever" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8317 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WEDFX_EDA_TOOL_AUTO_MISMATCH" "Precision Synthesis Custom " "Warning: Detecting \"Precision Synthesis\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"Custom\"" {  } {  } 0 0 "Detecting \"%1!s!\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/others/maxplus2/s_or8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/others/maxplus2/s_or8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 s_or8 " "Info: Found entity 1: s_or8" {  } { { "s_or8.tdf" "" { Text "d:/altera/quartus51/libraries/others/maxplus2/s_or8.tdf" 2 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "s_or8 reciever_8_:U_reciever\|s_or8:n7b " "Info: Elaborating entity \"s_or8\" for hierarchy \"reciever_8_:U_reciever\|s_or8:n7b\"" {  } { { "FPGA_Project2.edn" "n7b" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5376 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/others/maxplus2/s_or9.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/others/maxplus2/s_or9.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 s_or9 " "Info: Found entity 1: s_or9" {  } { { "s_or9.tdf" "" { Text "d:/altera/quartus51/libraries/others/maxplus2/s_or9.tdf" 2 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "s_or9 reciever_8_:U_reciever\|s_or9:n7c " "Info: Elaborating entity \"s_or9\" for hierarchy \"reciever_8_:U_reciever\|s_or9:n7c\"" {  } { { "FPGA_Project2.edn" "n7c" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5377 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "transfer_8_ transfer_8_:U_transfer " "Info: Elaborating entity \"transfer_8_\" for hierarchy \"transfer_8_:U_transfer\"" {  } { { "FPGA_Project2.edn" "U_transfer" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8323 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WEDFX_EDA_TOOL_AUTO_MISMATCH" "Precision Synthesis Custom " "Warning: Detecting \"Precision Synthesis\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"Custom\"" {  } {  } 0 0 "Detecting \"%1!s!\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"%2!s!\"" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "200 " "Info: Ignored 200 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "200 " "Info: Ignored 200 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_31 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_31\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4524 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Info" "ICDB_SGATE_CDB_INFO_USING_PWRUP_DC" "configurable_u3:U3\|StartUpCounter_3 High " "Info: Power-up level of register \"configurable_u3:U3\|StartUpCounter_3\" is not specified -- using power-up level of High to minimize register" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7865 24 0 } }  } 0 0 "Power-up level of register \"%1!s!\" is not specified -- using power-up level of %2!s! to minimize register" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "configurable_u3:U3\|StartUpCounter_3 data_in VCC " "Warning: Reduced register \"configurable_u3:U3\|StartUpCounter_3\" with stuck data_in port to stuck value VCC" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7865 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_19 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_19\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4484 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_18 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_18\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4486 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_17 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_17\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4488 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_16 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_16\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4490 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_15 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_15\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4492 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_14 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_14\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4494 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_13 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_13\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4496 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}
{ "Warning" "WCDB_SGATE_CDB_WARN_TRIVIAL_REG" "baud:U_baud\|cnt_12 data_in GND " "Warning: Reduced register \"baud:U_baud\|cnt_12\" with stuck data_in port to stuck value GND" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4498 24 0 } }  } 0 0 "Reduced register \"%1!s!\" with stuck %2!s! port to stuck value %3!s!" 0 0}