fpga_project2.map.qmsg

此RS232通信协议用VHDL语言实现

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_ configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:control_register " "Info: Elaborating entity \"configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_\" for hierarchy \"configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:control_register\"" {  } { { "FPGA_Project2.edn" "control_register" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7875 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WEDFX_EDA_TOOL_AUTO_MISMATCH" "Precision Synthesis Custom " "Warning: Detecting \"Precision Synthesis\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"Custom\"" {  } {  } 0 0 "Detecting \"%1!s!\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/LPM_ADD_SUB.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/LPM_ADD_SUB.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "LPM_ADD_SUB.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ADD_SUB.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ADD_SUB configurable_u3:U3\|LPM_ADD_SUB:i141 " "Info: Elaborating entity \"LPM_ADD_SUB\" for hierarchy \"configurable_u3:U3\|LPM_ADD_SUB:i141\"" {  } { { "FPGA_Project2.edn" "i141" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7881 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore configurable_u3:U3\|LPM_ADD_SUB:i141\|addcore:adder " "Info: Elaborating entity \"addcore\" for hierarchy \"configurable_u3:U3\|LPM_ADD_SUB:i141\|addcore:adder\"" {  } { { "LPM_ADD_SUB.tdf" "adder" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ADD_SUB.tdf" 266 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_csnbuffer configurable_u3:U3\|LPM_ADD_SUB:i141\|addcore:adder\|a_csnbuffer:oflow_node " "Info: Elaborating entity \"a_csnbuffer\" for hierarchy \"configurable_u3:U3\|LPM_ADD_SUB:i141\|addcore:adder\|a_csnbuffer:oflow_node\"" {  } { { "addcore.tdf" "oflow_node" { Text "d:/altera/quartus51/libraries/megafunctions/addcore.tdf" 94 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altshift configurable_u3:U3\|LPM_ADD_SUB:i141\|altshift:result_ext_latency_ffs " "Info: Elaborating entity \"altshift\" for hierarchy \"configurable_u3:U3\|LPM_ADD_SUB:i141\|altshift:result_ext_latency_ffs\"" {  } { { "LPM_ADD_SUB.tdf" "result_ext_latency_ffs" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ADD_SUB.tdf" 284 2 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "LPM_ADD_SUB configurable_u3:U3\|LPM_ADD_SUB:i142 " "Info: Elaborating entity \"LPM_ADD_SUB\" for hierarchy \"configurable_u3:U3\|LPM_ADD_SUB:i142\"" {  } { { "FPGA_Project2.edn" "i142" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7886 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addcore configurable_u3:U3\|LPM_ADD_SUB:i142\|addcore:adder " "Info: Elaborating entity \"addcore\" for hierarchy \"configurable_u3:U3\|LPM_ADD_SUB:i142\|addcore:adder\"" {  } { { "LPM_ADD_SUB.tdf" "adder" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_ADD_SUB.tdf" 266 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_ configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length " "Info: Elaborating entity \"configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_\" for hierarchy \"configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_:RegisterInput_Length\"" {  } { { "FPGA_Project2.edn" "RegisterInput_Length" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7898 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WEDFX_EDA_TOOL_AUTO_MISMATCH" "Precision Synthesis Custom " "Warning: Detecting \"Precision Synthesis\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"Custom\"" {  } {  } 0 0 "Detecting \"%1!s!\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_1_ configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_1_:RegisterOutput_Value " "Info: Elaborating entity \"configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_1_\" for hierarchy \"configurable_u3:U3\|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_1_:RegisterOutput_Value\"" {  } { { "FPGA_Project2.edn" "RegisterOutput_Value" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7896 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WEDFX_EDA_TOOL_AUTO_MISMATCH" "Precision Synthesis Custom " "Warning: Detecting \"Precision Synthesis\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"Custom\"" {  } {  } 0 0 "Detecting \"%1!s!\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "configurable_u3DIGITAL_IO_TAPCONTROLLER configurable_u3:U3\|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1 " "Info: Elaborating entity \"configurable_u3DIGITAL_IO_TAPCONTROLLER\" for hierarchy \"configurable_u3:U3\|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1\"" {  } { { "FPGA_Project2.edn" "TAP1" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7879 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WEDFX_EDA_TOOL_AUTO_MISMATCH" "Precision Synthesis Custom " "Warning: Detecting \"Precision Synthesis\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"Custom\"" {  } {  } 0 0 "Detecting \"%1!s!\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "configurable_u3DIGITAL_IO_DRNOOUT_32_ configurable_u3:U3\|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1\|configurable_u3DIGITAL_IO_DRNOOUT_32_:id_reg_unit " "Info: Elaborating entity \"configurable_u3DIGITAL_IO_DRNOOUT_32_\" for hierarchy \"configurable_u3:U3\|configurable_u3DIGITAL_IO_TAPCONTROLLER:TAP1\|configurable_u3DIGITAL_IO_DRNOOUT_32_:id_reg_unit\"" {  } { { "FPGA_Project2.edn" "id_reg_unit" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7306 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WEDFX_EDA_TOOL_AUTO_MISMATCH" "Precision Synthesis Custom " "Warning: Detecting \"Precision Synthesis\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"Custom\"" {  } {  } 0 0 "Detecting \"%1!s!\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "baud baud:U_baud " "Info: Elaborating entity \"baud\" for hierarchy \"baud:U_baud\"" {  } { { "FPGA_Project2.edn" "U_baud" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8325 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WEDFX_EDA_TOOL_AUTO_MISMATCH" "Precision Synthesis Custom " "Warning: Detecting \"Precision Synthesis\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"Custom\"" {  } {  } 0 0 "Detecting \"%1!s!\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/altera/quartus51/libraries/megafunctions/LPM_COMPARE.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/altera/quartus51/libraries/megafunctions/LPM_COMPARE.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_compare " "Info: Found entity 1: lpm_compare" {  } { { "LPM_COMPARE.tdf" "" { Text "d:/altera/quartus51/libraries/megafunctions/LPM_COMPARE.tdf" 264 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}