fpga_project2.map.qmsg

此RS232通信协议用VHDL语言实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 1991-2005 Altera Corporation. All rights reserved. " "Info: Copyright (C) 1991-2005 Altera Corporation. All rights reserved." {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Altera Corporation's design tools, logic functions  " "Info: Your use of Altera Corporation's design tools, logic functions " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic  " "Info: and other software and tools, and its AMPP partner logic " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files any of the foregoing  " "Info: functions, and any output files any of the foregoing " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any  " "Info: (including device programming or simulation files), and any " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject  " "Info: associated documentation or information are expressly subject " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Altera Program License  " "Info: to the terms and conditions of the Altera Program License " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, Altera MegaCore Function License  " "Info: Subscription Agreement, Altera MegaCore Function License " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Agreement, or other applicable license agreement, including,  " "Info: Agreement, or other applicable license agreement, including, " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "without limitation, that your use is for the sole purpose of  " "Info: without limitation, that your use is for the sole purpose of " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "programming logic devices manufactured by Altera and sold by  " "Info: programming logic devices manufactured by Altera and sold by " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Altera or its authorized distributors.  Please refer to the  " "Info: Altera or its authorized distributors.  Please refer to the " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable agreement for further details. " "Info: applicable agreement for further details." {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 30 13:49:46 2008 " "Info: Processing started: Wed Jul 30 13:49:46 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map FPGA_Project2 " "Info: Command: quartus_map FPGA_Project2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FPGA_Project2.edn 10 10 " "Info: Found 10 design units, including 10 entities, in source file FPGA_Project2.edn" { { "Info" "ISGN_ENTITY_NAME" "1 baud " "Info: Found entity 1: baud" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4424 9 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 configurable_u3 " "Info: Found entity 2: configurable_u3" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7821 9 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_ " "Info: Found entity 3: configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_16_" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 3495 9 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_1_ " "Info: Found entity 4: configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_1_" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 605 9 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_ " "Info: Found entity 5: configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 116 9 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 configurable_u3DIGITAL_IO_DRNOOUT_32_ " "Info: Found entity 6: configurable_u3DIGITAL_IO_DRNOOUT_32_" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 2609 9 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 configurable_u3DIGITAL_IO_TAPCONTROLLER " "Info: Found entity 7: configurable_u3DIGITAL_IO_TAPCONTROLLER" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 7146 9 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 FPGA_Project2 " "Info: Found entity 8: FPGA_Project2" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8303 9 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 reciever_8_ " "Info: Found entity 9: reciever_8_" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5309 9 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 transfer_8_ " "Info: Found entity 10: transfer_8_" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 709 9 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "FRQCNT2.VQM 14 14 " "Info: Found 14 design units, including 14 entities, in source file FRQCNT2.VQM" { { "Info" "ISGN_ENTITY_NAME" "1 FRQCNT2_DRNOOUT " "Info: Found entity 1: FRQCNT2_DRNOOUT" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 26 23 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "2 FRQCNT2_TAPCONTROLLER " "Info: Found entity 2: FRQCNT2_TAPCONTROLLER" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 466 29 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "3 FRQCNT2_DIVIDER " "Info: Found entity 3: FRQCNT2_DIVIDER" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 1018 23 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "4 FRQCNT2_DIVIDER_1 " "Info: Found entity 4: FRQCNT2_DIVIDER_1" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 1803 25 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "5 FRQCNT2_ENGINE_cell_currentstate_0_5__h_1 " "Info: Found entity 5: FRQCNT2_ENGINE_cell_currentstate_0_5__h_1" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 2588 49 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "6 FRQCNT2_ENGINE " "Info: Found entity 6: FRQCNT2_ENGINE" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 2708 22 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "7 FRQCNT2_ENGINE_cell_currentstate_0_5__h_2 " "Info: Found entity 7: FRQCNT2_ENGINE_cell_currentstate_0_5__h_2" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 4957 49 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "8 FRQCNT2_ENGINE_1 " "Info: Found entity 8: FRQCNT2_ENGINE_1" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 5077 24 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "9 FRQCNT2_DATAREG_INOUT_WRZ1 " "Info: Found entity 9: FRQCNT2_DATAREG_INOUT_WRZ1" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 7326 34 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "10 FRQCNT2_DATAREG_INOUT_WRZ0 " "Info: Found entity 10: FRQCNT2_DATAREG_INOUT_WRZ0" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 7554 34 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "11 FRQCNT2_DATAREG_INOUT_WRZ0_1 " "Info: Found entity 11: FRQCNT2_DATAREG_INOUT_WRZ0_1" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 8860 36 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "12 FRQCNT2_DATAREG_INOUT_WRZ1_1 " "Info: Found entity 12: FRQCNT2_DATAREG_INOUT_WRZ1_1" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10166 36 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "13 FRQCNT2_TOP " "Info: Found entity 13: FRQCNT2_TOP" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10461 19 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "14 FRQCNT2 " "Info: Found entity 14: FRQCNT2" {  } { { "FRQCNT2.VQM" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 11274 15 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "FPGA_Project2 " "Info: Elaborating entity \"FPGA_Project2\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WEDFX_EDA_TOOL_AUTO_MISMATCH" "Precision Synthesis Custom " "Warning: Detecting \"Precision Synthesis\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"Custom\"" {  } {  } 0 0 "Detecting \"%1!s!\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2 FRQCNT2:U2 " "Info: Elaborating entity \"FRQCNT2\" for hierarchy \"FRQCNT2:U2\"" {  } { { "FPGA_Project2.edn" "U2" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8321 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_TOP FRQCNT2:U2\|FRQCNT2_TOP:M_FC " "Info: Elaborating entity \"FRQCNT2_TOP\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\"" {  } { { "FRQCNT2.VQM" "M_FC" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 11329 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_TAPCONTROLLER FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1 " "Info: Elaborating entity \"FRQCNT2_TAPCONTROLLER\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\"" {  } { { "FRQCNT2.VQM" "TAP1" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10669 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_DRNOOUT FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|FRQCNT2_DRNOOUT:id_reg_unit " "Info: Elaborating entity \"FRQCNT2_DRNOOUT\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_TAPCONTROLLER:TAP1\|FRQCNT2_DRNOOUT:id_reg_unit\"" {  } { { "FRQCNT2.VQM" "id_reg_unit" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 1013 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_DIVIDER FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DIVIDER:PD1 " "Info: Elaborating entity \"FRQCNT2_DIVIDER\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DIVIDER:PD1\"" {  } { { "FRQCNT2.VQM" "PD1" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10706 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_DIVIDER_1 FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DIVIDER_1:PD2 " "Info: Elaborating entity \"FRQCNT2_DIVIDER_1\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DIVIDER_1:PD2\"" {  } { { "FRQCNT2.VQM" "PD2" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10743 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_ENGINE FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1 " "Info: Elaborating entity \"FRQCNT2_ENGINE\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\"" {  } { { "FRQCNT2.VQM" "FR1" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10849 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_ENGINE_cell_currentstate_0_5__h_1 FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|FRQCNT2_ENGINE_cell_currentstate_0_5__h_1:currentstate_h " "Info: Elaborating entity \"FRQCNT2_ENGINE_cell_currentstate_0_5__h_1\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE:FR1\|FRQCNT2_ENGINE_cell_currentstate_0_5__h_1:currentstate_h\"" {  } { { "FRQCNT2.VQM" "currentstate_h" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 4951 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_ENGINE_1 FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE_1:FR2 " "Info: Elaborating entity \"FRQCNT2_ENGINE_1\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE_1:FR2\"" {  } { { "FRQCNT2.VQM" "FR2" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10955 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_ENGINE_cell_currentstate_0_5__h_2 FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE_1:FR2\|FRQCNT2_ENGINE_cell_currentstate_0_5__h_2:currentstate_h " "Info: Elaborating entity \"FRQCNT2_ENGINE_cell_currentstate_0_5__h_2\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_ENGINE_1:FR2\|FRQCNT2_ENGINE_cell_currentstate_0_5__h_2:currentstate_h\"" {  } { { "FRQCNT2.VQM" "currentstate_h" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 7320 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_DATAREG_INOUT_WRZ1 FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1:control_register " "Info: Elaborating entity \"FRQCNT2_DATAREG_INOUT_WRZ1\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1:control_register\"" {  } { { "FRQCNT2.VQM" "control_register" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 10971 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_DATAREG_INOUT_WRZ0 FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ0:user1_register " "Info: Elaborating entity \"FRQCNT2_DATAREG_INOUT_WRZ0\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ0:user1_register\"" {  } { { "FRQCNT2.VQM" "user1_register" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 11110 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_DATAREG_INOUT_WRZ0_1 FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ0_1:user2_register " "Info: Elaborating entity \"FRQCNT2_DATAREG_INOUT_WRZ0_1\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ0_1:user2_register\"" {  } { { "FRQCNT2.VQM" "user2_register" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 11249 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "FRQCNT2_DATAREG_INOUT_WRZ1_1 FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register " "Info: Elaborating entity \"FRQCNT2_DATAREG_INOUT_WRZ1_1\" for hierarchy \"FRQCNT2:U2\|FRQCNT2_TOP:M_FC\|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register\"" {  } { { "FRQCNT2.VQM" "user3_register" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FRQCNT2.VQM" 11269 3 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "configurable_u3 configurable_u3:U3 " "Info: Elaborating entity \"configurable_u3\" for hierarchy \"configurable_u3:U3\"" {  } { { "FPGA_Project2.edn" "U3" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8319 16 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WEDFX_EDA_TOOL_AUTO_MISMATCH" "Precision Synthesis Custom " "Warning: Detecting \"Precision Synthesis\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"Custom\"" {  } {  } 0 0 "Detecting \"%1!s!\" as EDA design entry or synthesis tool that generated EDIF Input file, but EDA tool is specified as \"%2!s!\"" 0 0}