fpga_project2.fit.qmsg

此RS232通信协议用VHDL语言实现

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Copyright (C) 1991-2005 Altera Corporation. All rights reserved. " "Info: Copyright (C) 1991-2005 Altera Corporation. All rights reserved." {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Your use of Altera Corporation's design tools, logic functions  " "Info: Your use of Altera Corporation's design tools, logic functions " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "and other software and tools, and its AMPP partner logic  " "Info: and other software and tools, and its AMPP partner logic " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "functions, and any output files any of the foregoing  " "Info: functions, and any output files any of the foregoing " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "(including device programming or simulation files), and any  " "Info: (including device programming or simulation files), and any " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "associated documentation or information are expressly subject  " "Info: associated documentation or information are expressly subject " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "to the terms and conditions of the Altera Program License  " "Info: to the terms and conditions of the Altera Program License " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Subscription Agreement, Altera MegaCore Function License  " "Info: Subscription Agreement, Altera MegaCore Function License " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Agreement, or other applicable license agreement, including,  " "Info: Agreement, or other applicable license agreement, including, " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "without limitation, that your use is for the sole purpose of  " "Info: without limitation, that your use is for the sole purpose of " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "programming logic devices manufactured by Altera and sold by  " "Info: programming logic devices manufactured by Altera and sold by " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "Altera or its authorized distributors.  Please refer to the  " "Info: Altera or its authorized distributors.  Please refer to the " {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_LEGAL" "applicable agreement for further details. " "Info: applicable agreement for further details." {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jul 30 13:50:05 2008 " "Info: Processing started: Wed Jul 30 13:50:05 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit FPGA_Project2 " "Info: Command: quartus_fit FPGA_Project2" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "IMPP_MPP_USER_DEVICE" "FPGA_Project2 EP1C12Q240C6 " "Info: Selected device EP1C12Q240C6 for design \"FPGA_Project2\"" {  } {  } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0}
{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" {  } {  } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0}
{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1C6Q240C6 " "Info: Device EP1C6Q240C6 is compatible" {  } {  } 2 0 "Device %1!s! is compatible" 0 0}  } {  } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1 MHz " "Info: Assuming a global fmax requirement of 1 MHz" {  } {  } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" {  } {  } 0 0 "Not setting a global %1!s! requirement" 0 0}  } {  } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0}
{ "Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Info: Performing register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Performing register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Info: Completed register packing on registers with non-logic cell location assignments" {  } {  } 0 0 "Completed register packing on registers with non-logic cell location assignments" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "CLK_REF Global clock in PIN 152 " "Info: Automatically promoted signal \"CLK_REF\" to use Global clock in PIN 152" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8305 12 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "JTAG_NEXUS_TCK Global clock " "Info: Automatically promoted signal \"JTAG_NEXUS_TCK\" to use Global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8306 12 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "JTAG_NEXUS_TCK " "Info: Pin \"JTAG_NEXUS_TCK\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 8306 12 0 } } { "d:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "JTAG_NEXUS_TCK" } } } } { "d:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "d:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "FPGA_Project2" "UNKNOWN" "V1" "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/db/FPGA_Project2.quartus_db" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/" "" "" { JTAG_NEXUS_TCK } "NODE_NAME" } "" } } { "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" { Floorplan "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.fld" "" "" { JTAG_NEXUS_TCK } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "baud:U_baud\|INST_bclk Global clock " "Info: Automatically promoted signal \"baud:U_baud\|INST_bclk\" to use Global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 4528 16 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "reciever_8_:U_reciever\|INST_r_ready Global clock " "Info: Automatically promoted some destinations of signal \"reciever_8_:U_reciever\|INST_r_ready\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "reciever_8_:U_reciever\|INST_r_ready " "Info: Destination \"reciever_8_:U_reciever\|INST_r_ready\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5571 16 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|state_x_idle " "Info: Destination \"transfer_8_:U_transfer\|state_x_idle\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 1019 16 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|n7s~11 " "Info: Destination \"transfer_8_:U_transfer\|n7s~11\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 809 16 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "transfer_8_:U_transfer\|state_x_start " "Info: Destination \"transfer_8_:U_transfer\|state_x_start\" may be non-global or may not use global clock" {  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 931 16 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "FPGA_Project2.edn" "" { Text "E:/xuxing/学习资料/Altium翻译/my example/rs232_version2/ProjectOutputs/rs232_v2/FPGA_Project2.edn" 5571 16 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}