fpga_project2.hif

此RS232通信协议用VHDL语言实现

Version 5.1 Build 176 10/26/2005 SJ Full Version
33
1714
OFF
OFF
OFF
OFF
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
C:/PROGRAM FILES/ALTIUM DESIGNER SUMMER 08/LIBRARY/EDIF/Altium.LMF
-- Start Partition --
-- End Partition --
# entity
FPGA_Project2
# storage
db|FPGA_Project2.(0).cnf
db|FPGA_Project2.(0).cnf
# case_insensitive
# source_file
FPGA_Project2.edn
c9e89356cfef4915188dc7757a55f224
8
# hierarchies {
|
}
# end
# entity
FRQCNT2
# storage
db|FPGA_Project2.(1).cnf
db|FPGA_Project2.(1).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2
}
# end
# entity
FRQCNT2_TOP
# storage
db|FPGA_Project2.(2).cnf
db|FPGA_Project2.(2).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC
}
# end
# entity
FRQCNT2_TAPCONTROLLER
# storage
db|FPGA_Project2.(3).cnf
db|FPGA_Project2.(3).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1
}
# end
# entity
FRQCNT2_DRNOOUT
# storage
db|FPGA_Project2.(4).cnf
db|FPGA_Project2.(4).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_TAPCONTROLLER:TAP1|FRQCNT2_DRNOOUT:id_reg_unit
}
# end
# entity
FRQCNT2_DIVIDER
# storage
db|FPGA_Project2.(5).cnf
db|FPGA_Project2.(5).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_DIVIDER:PD1
}
# end
# entity
FRQCNT2_DIVIDER_1
# storage
db|FPGA_Project2.(6).cnf
db|FPGA_Project2.(6).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_DIVIDER_1:PD2
}
# end
# entity
FRQCNT2_ENGINE
# storage
db|FPGA_Project2.(7).cnf
db|FPGA_Project2.(7).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_ENGINE:FR1
}
# end
# entity
FRQCNT2_ENGINE_cell_currentstate_0_5__h_1
# storage
db|FPGA_Project2.(8).cnf
db|FPGA_Project2.(8).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_ENGINE:FR1|FRQCNT2_ENGINE_cell_currentstate_0_5__h_1:currentstate_h
}
# end
# entity
FRQCNT2_ENGINE_1
# storage
db|FPGA_Project2.(9).cnf
db|FPGA_Project2.(9).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_ENGINE_1:FR2
}
# end
# entity
FRQCNT2_ENGINE_cell_currentstate_0_5__h_2
# storage
db|FPGA_Project2.(10).cnf
db|FPGA_Project2.(10).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_ENGINE_1:FR2|FRQCNT2_ENGINE_cell_currentstate_0_5__h_2:currentstate_h
}
# end
# entity
FRQCNT2_DATAREG_INOUT_WRZ1
# storage
db|FPGA_Project2.(11).cnf
db|FPGA_Project2.(11).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_DATAREG_INOUT_WRZ1:control_register
}
# end
# entity
FRQCNT2_DATAREG_INOUT_WRZ0
# storage
db|FPGA_Project2.(12).cnf
db|FPGA_Project2.(12).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_DATAREG_INOUT_WRZ0:user1_register
}
# end
# entity
FRQCNT2_DATAREG_INOUT_WRZ0_1
# storage
db|FPGA_Project2.(13).cnf
db|FPGA_Project2.(13).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_DATAREG_INOUT_WRZ0_1:user2_register
}
# end
# entity
FRQCNT2_DATAREG_INOUT_WRZ1_1
# storage
db|FPGA_Project2.(14).cnf
db|FPGA_Project2.(14).cnf
# case_sensitive
# source_file
FRQCNT2.VQM
8fbfd826e4411f8f6f46fcbc57e1ab9
25
# hierarchies {
FRQCNT2:U2|FRQCNT2_TOP:M_FC|FRQCNT2_DATAREG_INOUT_WRZ1_1:user3_register
}
# end
# entity
configurable_u3
# storage
db|FPGA_Project2.(15).cnf
db|FPGA_Project2.(15).cnf
# case_insensitive
# source_file
FPGA_Project2.edn
c9e89356cfef4915188dc7757a55f224
8
# hierarchies {
configurable_u3:U3
}
# end
# entity
configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_
# storage
db|FPGA_Project2.(16).cnf
db|FPGA_Project2.(16).cnf
# case_insensitive
# source_file
FPGA_Project2.edn
c9e89356cfef4915188dc7757a55f224
8
# hierarchies {
configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:control_register
configurable_u3:U3|configurable_u3DIGITAL_IO_DATAREG_INOUT_WR_8_:RegisterInput_Value
}
# end
# entity
lpm_add_sub
# storage
db|FPGA_Project2.(17).cnf
db|FPGA_Project2.(17).cnf
# case_insensitive
# source_file
d:|altera|quartus51|libraries|megafunctions|LPM_ADD_SUB.tdf
6d69e5f6592ac38b99b31695315abe8
6
# user_parameter {
LPM_WIDTH
1
PARAMETER_UNKNOWN
USR
LPM_REPRESENTATION
SIGNED
PARAMETER_UNKNOWN
DEF
LPM_DIRECTION
ADD
PARAMETER_UNKNOWN
USR
ONE_INPUT_IS_CONSTANT
NO
PARAMETER_UNKNOWN
DEF
LPM_PIPELINE
0
PARAMETER_UNKNOWN
DEF
MAXIMIZE_SPEED
5
PARAMETER_UNKNOWN
DEF
REGISTERED_AT_END
0
PARAMETER_UNKNOWN
DEF
OPTIMIZE_FOR_SPEED
5
PARAMETER_UNKNOWN
USR
USE_CS_BUFFERS
1
PARAMETER_UNKNOWN
DEF
CARRY_CHAIN
MANUAL
PARAMETER_UNKNOWN
USR
CARRY_CHAIN_LENGTH
48
CARRY_CHAIN_LENGTH
USR
DEVICE_FAMILY
Cyclone
PARAMETER_UNKNOWN