configurable_u1digital_io_datareg_inout_wr_1__body.blf

来自「此RS232通信协议用VHDL语言实现」· BLF 代码 · 共 37 行

.model configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_1_
.inputs Rst
.inputs ResetValue<0>
.inputs clk
.inputs clken
.inputs enable
.inputs enable_write
.inputs si
.inputs shift
.inputs update
.inputs regin<0>
.outputs regout<0>
.outputs so
.names enable clken n4
11 1
.names regin<0> shift si n6
11- 1
-01 1
.names Rst ResetValue<0> n19
11 1
.loc Configurable_U1.VHD 609 regout<0>
.latch so regout<0> re clk 6 i30/preset i30/reset n13
.names n19 i30/preset
0 1
.names n21 i30/reset
0 1
.names update enable n12
11 1
.names n12 enable_write n13
11 1
.loc Configurable_U1.VHD 592 so
.latch n6 so re clk 2 n4
.names ResetValue<0> n20
0 1
.names Rst n20 n21
11 1