configurable_u1_body.blf

此RS232通信协议用VHDL语言实现

.names SignalGround16<0> RegisterInput_Value/ResetValue<8>
1 1
.names SignalGround16<0> RegisterInput_Value/ResetValue<7>
1 1
.names SignalGround16<0> RegisterInput_Value/ResetValue<6>
1 1
.names SignalGround16<0> RegisterInput_Value/ResetValue<5>
1 1
.names SignalGround16<0> RegisterInput_Value/ResetValue<4>
1 1
.names SignalGround16<0> RegisterInput_Value/ResetValue<3>
1 1
.names SignalGround16<0> RegisterInput_Value/ResetValue<2>
1 1
.names SignalGround16<0> RegisterInput_Value/ResetValue<1>
1 1
.names SignalGround16<0> RegisterInput_Value/ResetValue<0>
1 1
.names TCK RegisterInput_Value/clk
1 1
.names DR_Clock RegisterInput_Value/clken
1 1
.names User_Enable<1> RegisterInput_Value/enable
1 1
.names Enable_Write RegisterInput_Value/enable_write
1 1
.names TDI RegisterInput_Value/si
1 1
.names Shift_Capture RegisterInput_Value/shift
1 1
.names DR_Update RegisterInput_Value/update
1 1
.names RegisterInput_Value_Signal<9> RegisterInput_Value/regin<9>
1 1
.names RegisterInput_Value_Signal<8> RegisterInput_Value/regin<8>
1 1
.names RegisterInput_Value_Signal<7> RegisterInput_Value/regin<7>
1 1
.names RegisterInput_Value_Signal<6> RegisterInput_Value/regin<6>
1 1
.names RegisterInput_Value_Signal<5> RegisterInput_Value/regin<5>
1 1
.names RegisterInput_Value_Signal<4> RegisterInput_Value/regin<4>
1 1
.names RegisterInput_Value_Signal<3> RegisterInput_Value/regin<3>
1 1
.names RegisterInput_Value_Signal<2> RegisterInput_Value/regin<2>
1 1
.names RegisterInput_Value_Signal<1> RegisterInput_Value/regin<1>
1 1
.names RegisterInput_Value_Signal<0> RegisterInput_Value/regin<0>
1 1
.loc Configurable_U1.VHD 826
.subckt configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_16_ RegisterOutput_Length Rst=-RegisterOutput_Length/Rst ResetValue<15>=-RegisterOutput_Length/ResetValue<15> ResetValue<14>=-RegisterOutput_Length/ResetValue<14> ResetValue<13>=-RegisterOutput_Length/ResetValue<13> ResetValue<12>=-RegisterOutput_Length/ResetValue<12> ResetValue<11>=-RegisterOutput_Length/ResetValue<11> ResetValue<10>=-RegisterOutput_Length/ResetValue<10> ResetValue<9>=-RegisterOutput_Length/ResetValue<9> ResetValue<8>=-RegisterOutput_Length/ResetValue<8> ResetValue<7>=-RegisterOutput_Length/ResetValue<7> ResetValue<6>=-RegisterOutput_Length/ResetValue<6> ResetValue<5>=-RegisterOutput_Length/ResetValue<5> ResetValue<4>=-RegisterOutput_Length/ResetValue<4> ResetValue<3>=-RegisterOutput_Length/ResetValue<3> ResetValue<2>=-RegisterOutput_Length/ResetValue<2> ResetValue<1>=-RegisterOutput_Length/ResetValue<1> ResetValue<0>=-RegisterOutput_Length/ResetValue<0> clk=-RegisterOutput_Length/clk clken=-RegisterOutput_Length/clken enable=-RegisterOutput_Length/enable enable_write=-RegisterOutput_Length/enable_write si=-RegisterOutput_Length/si shift=-RegisterOutput_Length/shift update=-RegisterOutput_Length/update regin<15>=-RegisterOutput_Length/regin<15> regin<14>=-RegisterOutput_Length/regin<14> regin<13>=-RegisterOutput_Length/regin<13> regin<12>=-RegisterOutput_Length/regin<12> regin<11>=-RegisterOutput_Length/regin<11> regin<10>=-RegisterOutput_Length/regin<10> regin<9>=-RegisterOutput_Length/regin<9> regin<8>=-RegisterOutput_Length/regin<8> regin<7>=-RegisterOutput_Length/regin<7> regin<6>=-RegisterOutput_Length/regin<6> regin<5>=-RegisterOutput_Length/regin<5> regin<4>=-RegisterOutput_Length/regin<4> regin<3>=-RegisterOutput_Length/regin<3> regin<2>=-RegisterOutput_Length/regin<2> regin<1>=-RegisterOutput_Length/regin<1> regin<0>=-RegisterOutput_Length/regin<0> regout<15>=+$$COND36 regout<14>=+$$COND37 regout<13>=+$$COND38 regout<12>=+$$COND39 regout<11>=+$$COND40 regout<10>=+$$COND41 regout<9>=+$$COND42 regout<8>=+$$COND43 regout<7>=+$$COND44 regout<6>=+$$COND45 regout<5>=+$$COND46 regout<4>=+$$COND47 regout<3>=+$$COND48 regout<2>=+$$COND49 regout<1>=+$$COND50 regout<0>=+$$COND51 so=+User_SerialOut<2>
.names SignalGround16<0> RegisterOutput_Length/Rst
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<15>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<14>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<13>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<12>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<11>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<10>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<9>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<8>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<7>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<6>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<5>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<4>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<3>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<2>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<1>
1 1
.names SignalGround16<0> RegisterOutput_Length/ResetValue<0>
1 1
.names TCK RegisterOutput_Length/clk
1 1
.names DR_Clock RegisterOutput_Length/clken
1 1
.names User_Enable<2> RegisterOutput_Length/enable
1 1
.names Enable_Write RegisterOutput_Length/enable_write
1 1
.names TDI RegisterOutput_Length/si
1 1
.names Shift_Capture RegisterOutput_Length/shift
1 1
.names DR_Update RegisterOutput_Length/update
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<15>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<14>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<13>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<12>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<11>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<10>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<9>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<8>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<7>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<6>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<5>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<4>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<3>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<2>
1 1
.names SignalGround16<0> RegisterOutput_Length/regin<1>
1 1
.names id_code_signal<0> RegisterOutput_Length/regin<0>
1 1
.loc Configurable_U1.VHD 846
.subckt configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_1_ RegisterOutput_Value Rst=-RegisterOutput_Value/Rst ResetValue<0>=-RegisterOutput_Value/ResetValue<0> clk=-RegisterOutput_Value/clk clken=-RegisterOutput_Value/clken enable=-RegisterOutput_Value/enable enable_write=-RegisterOutput_Value/enable_write si=-RegisterOutput_Value/si shift=-RegisterOutput_Value/shift update=-RegisterOutput_Value/update regin<0>=-RegisterOutput_Value/regin<0> regout<0>=+RegisterOutput_Value_Signal<0> so=+User_SerialOut<3>
.names DefaultEnable RegisterOutput_Value/Rst
1 1
.names SignalGround16<0> RegisterOutput_Value/ResetValue<0>
1 1
.names TCK RegisterOutput_Value/clk
1 1
.names DR_Clock RegisterOutput_Value/clken
1 1
.names User_Enable<3> RegisterOutput_Value/enable
1 1
.names Enable_Write RegisterOutput_Value/enable_write
1 1
.names TDI RegisterOutput_Value/si
1 1
.names Shift_Capture RegisterOutput_Value/shift
1 1
.names DR_Update RegisterOutput_Value/update
1 1
.names RegisterOutput_Value_Signal<0> RegisterOutput_Value/regin<0>
1 1
.loc ../vhdl_packages/syn_unsi.vhd 118
.attrib lpm_direction 1 ADD
.attrib lpm_type 1 LPM_ADD_SUB
.attrib lpm_width 1 1
.subckt LPM_ADD_SUB i145 cin=-i145/cin dataa<0>=-i145/dataa<0> datab<0>=-i145/datab<0> result<0>=+n299 cout=+n344
.names add_95/n4 i145/cin
1 1
.names StartUpCounter<3> i145/dataa<0>
1 1
.names SignalGround16<0> i145/datab<0>
1 1
.names TRST n287
0 1
.loc Configurable_U1.VHD 887 StartUpCounter<3>
.latch n299 StartUpCounter<3> re TCK 4 i129/reset reduce_nor_92/n3
.names n287 i129/reset
0 1
.names reduce_nor_92/n3 n295
0 1
.loc Configurable_U1.VHD 887 DefaultEnable
.latch reduce_nor_92/n3 DefaultEnable re TCK 5 i143/reset n342
.names n287 i143/reset
0 1
.names StartUpCounter<0> n291
0 1
.names StartUpCounter<1> n292
0 1
.names StartUpCounter<2> n293
0 1
.names StartUpCounter<3> n294
0 1
.loc ../vhdl_packages/syn_unsi.vhd 118
.attrib lpm_direction 1 ADD
.attrib lpm_type 1 LPM_ADD_SUB
.attrib lpm_width 1 1
.subckt LPM_ADD_SUB i146 cin=-i146/cin dataa<0>=-i146/dataa<0> datab<0>=-i146/datab<0> result<0>=+n300 cout=+add_95/n4
.names add_95/n2 i146/cin
1 1
.names StartUpCounter<2> i146/dataa<0>
1 1
.names SignalGround16<0> i146/datab<0>
1 1
.names n341 n342
0 1
.loc ../vhdl_packages/syn_unsi.vhd 118
.attrib lpm_direction 1 ADD
.attrib lpm_type 1 LPM_ADD_SUB
.attrib lpm_width 1 1
.subckt LPM_ADD_SUB i147 cin=-i147/cin dataa<0>=-i147/dataa<0> datab<0>=-i147/datab<0> result<0>=+n301 cout=+add_95/n2
.names StartUpCounter<0> i147/cin
1 1
.names StartUpCounter<1> i147/dataa<0>
1 1
.names SignalGround16<0> i147/datab<0>
1 1
.names reduce_nor_92/n1 reduce_nor_92/n2 reduce_nor_92/n3
1- 1
-1 1
.names n295 n340 n341
11 1
.names User_Enable<3> n340
0 1
.loc Configurable_U1.VHD 887 StartUpCounter<0>
.latch n291 StartUpCounter<0> re TCK 4 i138/reset reduce_nor_92/n3
.names n287 i138/reset
0 1
.loc Configurable_U1.VHD 887 StartUpCounter<1>
.latch n301 StartUpCounter<1> re TCK 4 i135/reset reduce_nor_92/n3
.names n287 i135/reset
0 1
.loc Configurable_U1.VHD 887 StartUpCounter<2>
.latch n300 StartUpCounter<2> re TCK 4 i132/reset reduce_nor_92/n3
.names n287 i132/reset
0 1
.names Control_Out<0> Enable_Array<0> User_Enable<0>
11 1
.names Control_Out<1> Enable_Array<0> User_Enable<1>
11 1
.names Control_Out<2> Enable_Array<0> User_Enable<2>
11 1
.names Control_Out<3> Enable_Array<0> User_Enable<3>
11 1
.names Control_Out<7> Enable_Array<0> Enable_Write
11 1
.names User_SerialOut<3> User_Enable<3> Control_SerialOut n321
11- 1
-01 1
.names User_SerialOut<2> User_Enable<2> n321 n322
11- 1
-01 1
.names User_SerialOut<1> User_Enable<1> n322 n323
11- 1
-01 1
.names User_SerialOut<0> User_Enable<0> n323 Main_SerialOut
11- 1
-01 1
.names n291 n292 reduce_nor_92/n1
1- 1
-1 1