configurable_u1digital_io_datareg_inout_wr_16__body.blf

此RS232通信协议用VHDL语言实现

.model configurable_u1DIGITAL_IO_DATAREG_INOUT_WR_16_
.inputs Rst
.inputs ResetValue<15>
.inputs ResetValue<14>
.inputs ResetValue<13>
.inputs ResetValue<12>
.inputs ResetValue<11>
.inputs ResetValue<10>
.inputs ResetValue<9>
.inputs ResetValue<8>
.inputs ResetValue<7>
.inputs ResetValue<6>
.inputs ResetValue<5>
.inputs ResetValue<4>
.inputs ResetValue<3>
.inputs ResetValue<2>
.inputs ResetValue<1>
.inputs ResetValue<0>
.inputs clk
.inputs clken
.inputs enable
.inputs enable_write
.inputs si
.inputs shift
.inputs update
.inputs regin<15>
.inputs regin<14>
.inputs regin<13>
.inputs regin<12>
.inputs regin<11>
.inputs regin<10>
.inputs regin<9>
.inputs regin<8>
.inputs regin<7>
.inputs regin<6>
.inputs regin<5>
.inputs regin<4>
.inputs regin<3>
.inputs regin<2>
.inputs regin<1>
.inputs regin<0>
.outputs regout<15>
.outputs regout<14>
.outputs regout<13>
.outputs regout<12>
.outputs regout<11>
.outputs regout<10>
.outputs regout<9>
.outputs regout<8>
.outputs regout<7>
.outputs regout<6>
.outputs regout<5>
.outputs regout<4>
.outputs regout<3>
.outputs regout<2>
.outputs regout<1>
.outputs regout<0>
.outputs so
.loc Configurable_U1.VHD 609 regout<12>
.latch sh_reg<12> regout<12> re clk 6 i249/preset i249/reset n223
.names n136 i249/preset
0 1
.names n138 i249/reset
0 1
.loc Configurable_U1.VHD 609 regout<13>
.latch sh_reg<13> regout<13> re clk 6 i246/preset i246/reset n223
.names n132 i246/preset
0 1
.names n134 i246/reset
0 1
.loc Configurable_U1.VHD 609 regout<14>
.latch sh_reg<14> regout<14> re clk 6 i243/preset i243/reset n223
.names n128 i243/preset
0 1
.names n130 i243/reset
0 1
.names enable clken n220
11 1
.names shift n5
0 1
.names si n5 regin<15> n6
11- 1
-01 1
.names sh_reg<15> n5 regin<14> n7
11- 1
-01 1
.names sh_reg<14> n5 regin<13> n8
11- 1
-01 1
.names sh_reg<13> n5 regin<12> n9
11- 1
-01 1
.names sh_reg<12> n5 regin<11> n10
11- 1
-01 1
.names sh_reg<11> n5 regin<10> n11
11- 1
-01 1
.names sh_reg<10> n5 regin<9> n12
11- 1
-01 1
.names sh_reg<9> n5 regin<8> n13
11- 1
-01 1
.names sh_reg<8> n5 regin<7> n14
11- 1
-01 1
.names sh_reg<7> n5 regin<6> n15
11- 1
-01 1
.names sh_reg<6> n5 regin<5> n16
11- 1
-01 1
.names sh_reg<5> n5 regin<4> n17
11- 1
-01 1
.names sh_reg<4> n5 regin<3> n18
11- 1
-01 1
.names sh_reg<3> n5 regin<2> n19
11- 1
-01 1
.names sh_reg<2> n5 regin<1> n20
11- 1
-01 1
.names sh_reg<1> n5 regin<0> n21
11- 1
-01 1
.names Rst ResetValue<15> n124
11 1
.loc Configurable_U1.VHD 609 regout<15>
.latch sh_reg<15> regout<15> re clk 6 i240/preset i240/reset n223
.names n124 i240/preset
0 1
.names n126 i240/reset
0 1
.names update enable n57
11 1
.names n57 enable_write n223
11 1
.names Rst ResetValue<14> n128
11 1
.names Rst ResetValue<13> n132
11 1
.names Rst ResetValue<12> n136
11 1
.names Rst ResetValue<11> n140
11 1
.names Rst ResetValue<10> n144
11 1
.names Rst ResetValue<9> n148
11 1
.names Rst ResetValue<8> n152
11 1
.names Rst ResetValue<7> n156
11 1
.names Rst ResetValue<6> n160
11 1
.names Rst ResetValue<5> n164
11 1
.names Rst ResetValue<4> n168
11 1
.names Rst ResetValue<3> n172
11 1
.names Rst ResetValue<2> n176
11 1
.names Rst ResetValue<1> n180
11 1
.names Rst ResetValue<0> n184
11 1
.loc Configurable_U1.VHD 609 regout<11>
.latch sh_reg<11> regout<11> re clk 6 i252/preset i252/reset n223
.names n140 i252/preset
0 1
.names n142 i252/reset
0 1
.loc Configurable_U1.VHD 592 sh_reg<15>
.latch n6 sh_reg<15> re clk 2 n220
.loc Configurable_U1.VHD 592 so
.latch n21 so re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<1>
.latch n20 sh_reg<1> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<2>
.latch n19 sh_reg<2> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<3>
.latch n18 sh_reg<3> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<4>
.latch n17 sh_reg<4> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<5>
.latch n16 sh_reg<5> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<6>
.latch n15 sh_reg<6> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<7>
.latch n14 sh_reg<7> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<8>
.latch n13 sh_reg<8> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<9>
.latch n12 sh_reg<9> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<10>
.latch n11 sh_reg<10> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<11>
.latch n10 sh_reg<11> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<12>
.latch n9 sh_reg<12> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<13>
.latch n8 sh_reg<13> re clk 2 n220
.loc Configurable_U1.VHD 592 sh_reg<14>
.latch n7 sh_reg<14> re clk 2 n220
.names ResetValue<15> n125
0 1
.names Rst n125 n126
11 1
.names ResetValue<14> n129
0 1
.names Rst n129 n130
11 1
.names ResetValue<13> n133
0 1
.names Rst n133 n134
11 1
.names ResetValue<12> n137
0 1
.names Rst n137 n138
11 1
.names ResetValue<11> n141
0 1
.names Rst n141 n142
11 1
.names ResetValue<10> n145
0 1
.names Rst n145 n146
11 1
.names ResetValue<9> n149
0 1
.names Rst n149 n150
11 1
.names ResetValue<8> n153
0 1
.names Rst n153 n154
11 1
.names ResetValue<7> n157
0 1
.names Rst n157 n158
11 1
.names ResetValue<6> n161
0 1
.names Rst n161 n162
11 1
.names ResetValue<5> n165
0 1
.names Rst n165 n166
11 1
.names ResetValue<4> n169
0 1
.names Rst n169 n170
11 1
.names ResetValue<3> n173
0 1
.names Rst n173 n174
11 1
.names ResetValue<2> n177
0 1
.names Rst n177 n178
11 1
.names ResetValue<1> n181
0 1
.names Rst n181 n182
11 1
.names ResetValue<0> n185
0 1
.names Rst n185 n186
11 1
.loc Configurable_U1.VHD 609 regout<10>
.latch sh_reg<10> regout<10> re clk 6 i255/preset i255/reset n223
.names n144 i255/preset
0 1
.names n146 i255/reset
0 1
.loc Configurable_U1.VHD 609 regout<9>
.latch sh_reg<9> regout<9> re clk 6 i258/preset i258/reset n223
.names n148 i258/preset
0 1
.names n150 i258/reset
0 1
.loc Configurable_U1.VHD 609 regout<8>
.latch sh_reg<8> regout<8> re clk 6 i261/preset i261/reset n223
.names n152 i261/preset
0 1
.names n154 i261/reset
0 1
.loc Configurable_U1.VHD 609 regout<7>
.latch sh_reg<7> regout<7> re clk 6 i264/preset i264/reset n223
.names n156 i264/preset
0 1
.names n158 i264/reset
0 1
.loc Configurable_U1.VHD 609 regout<6>
.latch sh_reg<6> regout<6> re clk 6 i267/preset i267/reset n223
.names n160 i267/preset
0 1
.names n162 i267/reset
0 1
.loc Configurable_U1.VHD 609 regout<5>
.latch sh_reg<5> regout<5> re clk 6 i270/preset i270/reset n223
.names n164 i270/preset
0 1
.names n166 i270/reset
0 1
.loc Configurable_U1.VHD 609 regout<4>
.latch sh_reg<4> regout<4> re clk 6 i273/preset i273/reset n223
.names n168 i273/preset
0 1
.names n170 i273/reset
0 1
.loc Configurable_U1.VHD 609 regout<3>
.latch sh_reg<3> regout<3> re clk 6 i276/preset i276/reset n223
.names n172 i276/preset
0 1
.names n174 i276/reset
0 1
.loc Configurable_U1.VHD 609 regout<2>
.latch sh_reg<2> regout<2> re clk 6 i279/preset i279/reset n223
.names n176 i279/preset
0 1
.names n178 i279/reset
0 1
.loc Configurable_U1.VHD 609 regout<1>
.latch sh_reg<1> regout<1> re clk 6 i282/preset i282/reset n223
.names n180 i282/preset
0 1
.names n182 i282/reset
0 1
.loc Configurable_U1.VHD 609 regout<0>
.latch so regout<0> re clk 6 i285/preset i285/reset n223
.names n184 i285/preset
0 1
.names n186 i285/reset
0 1