receive.gyd

dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过.

Pin Freeze File:  version E.33

9510884 XC95108-7-PC84
clock S:PIN9
rxd S:PIN1
sbuf<0> S:PIN39
sbuf<1> S:PIN37
sbuf<2> S:PIN36
sbuf<3> S:PIN35
sbuf<4> S:PIN34
sbuf<5> S:PIN33
sbuf<6> S:PIN32
sbuf<7> S:PIN31


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.



PARTITION FB3_1 EXP0_
PARTITION FB3_8 clock_pluse clock_div_6 clock_div_5 clock_div_4
		 clock_div_0 clock_div_3 count_reg_3 count_reg_2
		 clock_div_1 N127 clock_div_2

PARTITION FB5_1 EXP1_ N124 N121 EXP2_
		 N118 N115 bit_cnt_3 N112
		 N109 bit_cnt_2 N106 bit_cnt_1
		 bit_cnt_0 count_reg_1 count_reg_0 rxd_start_reg
		 bit_collect_1 bit_collect_0