__projnav.log

dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过.

Starting: 'exewrap @__receive_2prj_exewrap.rsp'


Creating TCL Process
Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn receive.xst -ofn receive.syr'


Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn receive.xst -ofn receive.syr '


Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 0.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : receive.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : receive
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : receive
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : receive.prj
Compiling included source file 'receive.v'
Module <receive> compiled.
Continuing compilation of source file 'receive.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'receive.prj'
No errors in compilation
Analysis of file <receive.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <receive>.
Module <receive> is correct for synthesis.

Synthesizing Unit <receive>.
    Related source file is receive.v.
WARNING:Xst:646 - Signal <bit_collect<2>> is assigned but never used.
WARNING:Xst:646 - Signal <uart_buf<9>> is assigned but never used.
WARNING:Xst:646 - Signal <rxd_end> is assigned but never used.
    Found 7-bit comparator less for signal <$n0004> created at line 19.
    Found 4-bit comparator less for signal <$n0018> created at line 47.
    Found 4-bit adder for signal <$n0023> created at line 48.
    Found 4-bit comparator greater for signal <$n0024> created at line 69.
    Found 4-bit adder for signal <$old_bit_cnt_3>.
    Found 4-bit register for signal <bit_cnt>.
    Found 2-bit register for signal <bit_collect<1:0>>.
    Found 7-bit up counter for signal <clock_div>.
    Found 1-bit register for signal <clock_pluse>.
    Found 4-bit register for signal <count_reg>.
    Found 1-bit register for signal <rxd_start_reg>.
    Found 9-bit register for signal <uart_buf<8:0>>.
    Found 7 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred  21 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
	inferred   7 Multiplexer(s).
Unit <receive> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 15
  4-bit register                   : 2
  1-bit register                   : 13
# Counters                         : 1
  7-bit up counter                 : 1
# Multiplexers                     : 4
  2-to-1 multiplexer               : 4
# Adders/Subtractors               : 2
  4-bit adder                      : 2
# Comparators                      : 3
  7-bit comparator less            : 1
  4-bit comparator less            : 1
  4-bit comparator greater         : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <receive> ...
=========================================================================
Final Results
Output File Name                   : receive
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Comparators                      : 3
  7-bit comparator less            : 1
  4-bit comparator less            : 1
  4-bit comparator greater         : 1
# Xors                             : 12
  1-bit xor2                       : 12

Design Statistics
# Edif Instances                   : 248
# I/Os                             : 10

=========================================================================
CPU : 2.64 / 2.86 s | Elapsed : 3.00 / 3.00 s
 
--> 
EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.

Done: completed successfully.

Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp receive ngdbuild.rsp'


Creating TCL Process
Starting: 'ngdbuild -f ngdbuild.rsp'


Release 4.1WP3.x - ngdbuild E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc receive.ucf -p XC9500 receive.ngc
receive.ngd 

Reading NGO file "C:/WINDOWS/Desktop/receive/receive.ngc" ...
Reading component libraries for design expansion...
Running LogiBLOX expansion on symbol "clock_div_Madd__n0000_Mxor_Result_1"...
WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_1 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "clock_div_Madd_
_n0000_Mxor_Result_2"...
WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_2 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "clock_div_Madd_
_n0000_Mxor_Result_3"...
WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_3 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "clock_div_Madd_
_n0000_Mxor_Result_4"...
WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_4 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "clock_div_Madd__n0000_Mxor_Result_5"...
WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_5 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "clock_div_Madd_
_n0000_Mxor_Result_6"...
WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_6 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0023_Mxo
r_Result_1"...
WARNING:LBEngine:353 - Module Madd__n0023_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0023_Mxor_Re
sult_2"...
WARNING:LBEngine:353 - Module Madd__n0023_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0023_Mxor_Re
sult_3"...
WARNING:LBEngine:353 - Module Madd__n0023_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_bit_cnt_3
_Mxor_Result_1"...
WARNING:LBEngine:353 - Module Madd__old_bit_cnt_3_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_bit_cnt_3_Mxor_Result_2"...
WARNING:LBEngine:353 - Module Madd__old_bit_cnt_3_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_bit_cnt_3
_Mxor_Result_3"...
WARNING:LBEngine:353 - Module Madd__old_bit_cnt_3_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.
Annotating constraints to design from file "receive.ucf" ...

Checking timing specifications ...

Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "receive.ngd" ...

Writing NGDBUILD log file "receive.bld"...

NGDBUILD done.
Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.




Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -tcl -command _cpldfit.tcl'


Creating TCL Process
Starting: 'cpldfit -f _cpldfit.rsp receive.ngd'


Release 4.1WP3.x - X9K/XPLA Optimizer/Partitioner E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
Considering device XC95108-PC84.
Flattening design..
Timing optimization
Timing driven global resource optimization
General global resource optimization........
Re-checking device resources ...
Mapping a total of 27 equations into 6 function blocks...

Design receive has been optimized and fit into device XC95108-7-PC84.
Tcl _cpldfit.tcl detected that program 'cpldfit -f _cpldfit.rsp receive.ngd' completed successfully.


Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command hprep6 -i receive -r int -a -l receive.log -n receive '


Starting: 'hprep6 -i receive -r int -a -l receive.log -n receive '


Release 4.1WP3.x - Programming File Generator E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
EXEWRAP detected that program 'hprep6' completed successfully.

Done: completed successfully.

Launching: 'impact -f __impact.rsp'



ISE Auto-Make Log File
-----------------------

Updating: Assign Pins (ChipViewer)

Starting: 'exewrap -mode pipe -tapkeep -tcl -command _chipview.tcl'


Creating TCL Process
Starting: 'ChipView.bat -f receive.ngd -uc receive.ucf -dev XC95108-7-PC84'


Tcl _chipview.tcl detected that program 'ChipView.bat -f receive.ngd -uc receive.ucf -dev XC95108-7-PC84' completed successfully.




Starting: 'chkdate'


Tcl _chipview.tcl detected that program 'chkdate' completed successfully.

Existing implementation results (if any) will be retained.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_receive.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    receive.v
Writing receive.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.