receive.syr

dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过.

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
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--> Parameter overwrite set to YES
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : receive.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : receive
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : receive
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : receive.prj
Compiling included source file 'receive.v'
Module <receive> compiled.
Continuing compilation of source file 'receive.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'receive.prj'
No errors in compilation
Analysis of file <receive.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <receive>.
Module <receive> is correct for synthesis.

Synthesizing Unit <receive>.
    Related source file is receive.v.
WARNING:Xst:646 - Signal <bit_collect<2>> is assigned but never used.
WARNING:Xst:646 - Signal <uart_buf<9>> is assigned but never used.
WARNING:Xst:646 - Signal <rxd_end> is assigned but never used.
    Found 7-bit comparator less for signal <$n0004> created at line 19.
    Found 4-bit comparator less for signal <$n0018> created at line 47.
    Found 4-bit adder for signal <$n0023> created at line 48.
    Found 4-bit comparator greater for signal <$n0024> created at line 69.
    Found 4-bit adder for signal <$old_bit_cnt_3>.
    Found 4-bit register for signal <bit_cnt>.
    Found 2-bit register for signal <bit_collect<1:0>>.
    Found 7-bit up counter for signal <clock_div>.
    Found 1-bit register for signal <clock_pluse>.
    Found 4-bit register for signal <count_reg>.
    Found 1-bit register for signal <rxd_start_reg>.
    Found 9-bit register for signal <uart_buf<8:0>>.
    Found 7 1-bit 2-to-1 multiplexers.
    Summary:
	inferred   1 Counter(s).
	inferred  21 D-type flip-flop(s).
	inferred   2 Adder/Subtracter(s).
	inferred   3 Comparator(s).
	inferred   7 Multiplexer(s).
Unit <receive> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 15
  4-bit register                   : 2
  1-bit register                   : 13
# Counters                         : 1
  7-bit up counter                 : 1
# Multiplexers                     : 4
  2-to-1 multiplexer               : 4
# Adders/Subtractors               : 2
  4-bit adder                      : 2
# Comparators                      : 3
  7-bit comparator less            : 1
  4-bit comparator less            : 1
  4-bit comparator greater         : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <receive> ...
=========================================================================
Final Results
Output File Name                   : receive
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Comparators                      : 3
  7-bit comparator less            : 1
  4-bit comparator less            : 1
  4-bit comparator greater         : 1
# Xors                             : 12
  1-bit xor2                       : 12

Design Statistics
# Edif Instances                   : 248
# I/Os                             : 10

=========================================================================
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