📄 receive.rpt
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cpldfit: version E.33 Xilinx Inc.
Fitter Report
Design Name: receive Date: 11-26-2002, 9:44AM
Device Used: XC95108-7-PC84
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
27 /108 ( 25%) 125 /540 ( 23%) 27 /108 ( 25%) 10 /69 ( 14%) 41 /216 ( 18%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 1 1 | I/O : 9 54
Output : 8 8 | GCK/IO : 1 2
Bidirectional : 0 0 | GTS/IO : 0 2
GCK : 1 1 | GSR/IO : 0 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 10 10
MACROCELL RESOURCES:
Total Macrocells Available 108
Registered Macrocells 27
Non-registered Macrocell driving I/O 0
GLOBAL RESOURCES:
The complement of 'clock' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 27 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 27 macrocells used (MC).
End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin
Name Pt Used Mode Rate # Type Use
bit_cnt_0 3 8 FB5_13 STD (b) (b)
bit_cnt_1 3 9 FB5_12 STD 40 I/O (b)
bit_cnt_2 3 10 FB5_10 STD (b) (b)
bit_cnt_3 3 11 FB5_7 STD (b) (b)
bit_collect_0 3 8 FB5_18 STD (b) (b)
bit_collect_1 3 8 FB5_17 STD 44 I/O (b)
clock_div_0 2 5 FB3_12 STD 23 I/O (b)
clock_div_1 4 6 FB3_16 STD 26 I/O (b)
clock_div_2 5 7 FB3_18 STD (b) (b)
clock_div_3 3 7 FB3_13 STD (b) (b)
clock_div_4 2 6 FB3_11 STD 21 I/O (b)
clock_div_5 2 7 FB3_10 STD (b) (b)
clock_div_6 2 7 FB3_9 STD 20 I/O (b)
clock_pluse 2 4 FB3_8 STD 19 I/O (b)
count_reg_0 4 7 FB5_15 STD 43 I/O (b)
count_reg_1 4 7 FB5_14 STD 41 I/O (b)
count_reg_2 4 7 FB3_15 STD 25 I/O (b)
count_reg_3 4 7 FB3_14 STD 24 I/O (b)
rxd_start_reg 13 13 FB5_16 STD (b) (b)
sbuf<0> 7 14 FB5_11 STD FAST 39 I/O O
sbuf<1> 7 14 FB5_9 STD FAST 37 I/O O
sbuf<2> 7 14 FB5_8 STD FAST 36 I/O O
sbuf<3> 7 14 FB5_6 STD FAST 35 I/O O
sbuf<4> 7 14 FB5_5 STD FAST 34 I/O O
sbuf<5> 7 14 FB5_3 STD FAST 33 I/O O
sbuf<6> 7 14 FB5_2 STD FAST 32 I/O O
sbuf<7> 7 14 FB3_17 STD FAST 31 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
clock FB1_12 9 GCK/I/O GCK
rxd FB1_2 1 I/O I
End of Resources Used by Successfully Mapped Logic
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 0 0 0 0 0/0 12
FB2 0 0 0 0 0/0 12
FB3 11 21 21 37 1/0 12
FB4 0 0 0 0 0/0 11
FB5 16 20 20 88 7/0 11
FB6 0 0 0 0 0/0 11
---- ----- ----- -----
27 125 8/0 69
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O I
(unused) 0 0 0 5 FB1_3 2 I/O
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 3 I/O
(unused) 0 0 0 5 FB1_6 4 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 5 I/O
(unused) 0 0 0 5 FB1_9 6 I/O
(unused) 0 0 0 5 FB1_10 (b)
(unused) 0 0 0 5 FB1_11 7 I/O
(unused) 0 0 0 5 FB1_12 9 GCK/I/O GCK
(unused) 0 0 0 5 FB1_13 (b)
(unused) 0 0 0 5 FB1_14 10 GCK/I/O
(unused) 0 0 0 5 FB1_15 11 I/O
(unused) 0 0 0 5 FB1_16 12 GCK/I/O
(unused) 0 0 0 5 FB1_17 13 I/O
(unused) 0 0 0 5 FB1_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB2_1 (b)
(unused) 0 0 0 5 FB2_2 71 I/O
(unused) 0 0 0 5 FB2_3 72 I/O
(unused) 0 0 0 5 FB2_4 (b)
(unused) 0 0 0 5 FB2_5 74 GSR/I/O
(unused) 0 0 0 5 FB2_6 75 I/O
(unused) 0 0 0 5 FB2_7 (b)
(unused) 0 0 0 5 FB2_8 76 GTS/I/O
(unused) 0 0 0 5 FB2_9 77 GTS/I/O
(unused) 0 0 0 5 FB2_10 (b)
(unused) 0 0 0 5 FB2_11 79 I/O
(unused) 0 0 0 5 FB2_12 80 I/O
(unused) 0 0 0 5 FB2_13 (b)
(unused) 0 0 0 5 FB2_14 81 I/O
(unused) 0 0 0 5 FB2_15 82 I/O
(unused) 0 0 0 5 FB2_16 83 I/O
(unused) 0 0 0 5 FB2_17 84 I/O
(unused) 0 0 0 5 FB2_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining: 21/15
Number of signals used by logic mapping into function block: 21
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 /\1 4 FB3_1 (b) (b)
(unused) 0 0 0 5 FB3_2 14 I/O
(unused) 0 0 0 5 FB3_3 15 I/O
(unused) 0 0 0 5 FB3_4 (b)
(unused) 0 0 0 5 FB3_5 17 I/O
(unused) 0 0 0 5 FB3_6 18 I/O
(unused) 0 0 0 5 FB3_7 (b)
clock_pluse 2 0 0 3 FB3_8 STD 19 I/O (b)
clock_div_6 2 0 0 3 FB3_9 STD 20 I/O (b)
clock_div_5 2 0 0 3 FB3_10 STD (b) (b)
clock_div_4 2 0 0 3 FB3_11 STD 21 I/O (b)
clock_div_0 2 0 0 3 FB3_12 STD 23 I/O (b)
clock_div_3 3 0 0 2 FB3_13 STD (b) (b)
count_reg_3 4 0 0 1 FB3_14 STD 24 I/O (b)
count_reg_2 4 0 0 1 FB3_15 STD 25 I/O (b)
clock_div_1 4 0 \/1 0 FB3_16 STD 26 I/O (b)
sbuf<7> 7 2<- 0 0 FB3_17 STD 31 I/O O
clock_div_2 5 1<- /\1 0 FB3_18 STD (b) (b)
Signals Used by Logic in Function Block
1: N127.FBK.LFBK 8: bit_collect_1 15: clock_div_6.FBK.LFBK
2: rxd 9: clock_div_0.FBK.LFBK
16: clock_pluse.FBK.LFBK
3: bit_cnt_0 10: clock_div_1.FBK.LFBK
17: count_reg_0
4: bit_cnt_1 11: clock_div_2.FBK.LFBK
18: count_reg_1
5: bit_cnt_2 12: clock_div_3.FBK.LFBK
19: count_reg_2.FBK.LFBK
6: bit_cnt_3 13: clock_div_4.FBK.LFBK
20: count_reg_3.FBK.LFBK
7: bit_collect_0 14: clock_div_5.FBK.LFBK
21: rxd_start_reg
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
clock_pluse ...........XXXX......................... 4 4
clock_div_6 ........XXXXXXX......................... 7 7
clock_div_5 ........XXXXXXX......................... 7 7
clock_div_4 ........XXXXX.X......................... 6 6
clock_div_0 ........X..XXXX......................... 5 5
clock_div_3 ........XXXXXXX......................... 7 7
count_reg_3 .X.............XXXXXX................... 7 7
count_reg_2 .X.............XXXXXX................... 7 7
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