receive.bld

来自「dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过」· BLD 代码 · 共 47 行

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Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.Command Line: ngdbuild -dd _ngo -uc receive.ucf -p XC9500 receive.ngc
receive.ngd Reading NGO file "C:/WINDOWS/Desktop/receive/receive.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "clock_div_Madd__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_1 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "clock_div_Madd__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_2 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "clock_div_Madd__n0000_Mxor_Result_3"...WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_3 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "clock_div_Madd__n0000_Mxor_Result_4"...WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_4 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "clock_div_Madd__n0000_Mxor_Result_5"...WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_5 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "clock_div_Madd__n0000_Mxor_Result_6"...WARNING:LBEngine:353 - Module clock_div_Madd__n0000_Mxor_Result_6 : All styles
   for SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0023_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0023_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0023_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0023_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0023_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0023_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_bit_cnt_3_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__old_bit_cnt_3_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_bit_cnt_3_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__old_bit_cnt_3_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_bit_cnt_3_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__old_bit_cnt_3_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Annotating constraints to design from file "receive.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary:  Number of errors:     0  Number of warnings:   0Writing NGD file "receive.ngd" ...Writing NGDBUILD log file "receive.bld"...

receive.bld - 源码说明

本页面展示了「dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过.」中的 receive.bld 源码文件，采用 BLD 编程语言编写，共 47 行代码。您可以在线阅读完整代码内容，也可以返回资源详情页下载完整源码包进行本地学习和开发。

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