receive.pnx

dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过.

<?xml version='1.0' encoding='utf-8' ?>
<!DOCTYPE ibis [
<!ELEMENT ibis (part, pin+)>
<!ELEMENT part EMPTY>
<!ELEMENT pin EMPTY>
<!ATTLIST part
  arch   CDATA #REQUIRED
  device CDATA #REQUIRED
  spg    CDATA #REQUIRED
  pkg    CDATA #REQUIRED>
<!ATTLIST pin
  nm     CDATA #REQUIRED
  no     CDATA #REQUIRED
  iostd  (TTL|LVTTL|LVCMOS2|NA) "NA"
  sr     (SLOW|FAST|slow|fast) "SLOW">
]>
<ibis><part pkg="PC84" spg="-7" arch="xc9500" device="XC95108"/><pin nm="rxd" no="1"/><pin nm="clock" no="9"/><pin nm="sbuf&lt;0&gt;" no="39" sr="fast"/><pin nm="sbuf&lt;1&gt;" no="37" sr="fast"/><pin nm="sbuf&lt;2&gt;" no="36" sr="fast"/><pin nm="sbuf&lt;3&gt;" no="35" sr="fast"/><pin nm="sbuf&lt;4&gt;" no="34" sr="fast"/><pin nm="sbuf&lt;5&gt;" no="33" sr="fast"/><pin nm="sbuf&lt;6&gt;" no="32" sr="fast"/><pin nm="sbuf&lt;7&gt;" no="31" sr="fast"/></ibis>