📄 automake.log
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ISE Auto-Make Log File-----------------------
Updating: Configure Device (iMPACT)
Starting: 'exewrap @__send_2prj_exewrap.rsp'
Creating TCL ProcessDone: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn send.xst -ofn send.syr'
Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn send.xst -ofn send.syr 'Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format : VERILOGInput File Name : send.prj---- Target ParametersTarget Device : XC9500Output File Name : sendOutput Format : NGCTarget Technology : 9500---- Source OptionsTop Module Name : sendAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Flip-Flop Type : DMux Extraction : YESResource Sharing : YESComplex Clock Enable Extraction : YES---- Target OptionsAdd IO Buffers : YESEquivalent register Removal : YESMacro Generator : AutoMACRO Preserve : YESXOR Preserve : YES---- General OptionsOptimization Criterion : SpeedOptimization Effort : 1Check Attribute Syntax : YESKeep Hierarchy : YES---- Other Optionswysiwyg : NO========================================================================= Compiling source file : send.prjCompiling included source file 'send.v'Module <send> compiled.Continuing compilation of source file 'send.prj'Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'Continuing compilation of source file 'send.prj'No errors in compilationAnalysis of file <send.prj> succeeded. Starting Verilog synthesis. Analyzing top module <send>.Module <send> is correct for synthesis.Synthesizing Unit <send>. Related source file is send.v.WARNING:Xst:737 - Found 8-bit latch for signal <uart_buf>. Found 11-bit comparator less for signal <$n0001> created at line 16. Found 4-bit comparator less for signal <$n0006> created at line 52. Found 4-bit adder for signal <$n0017> created at line 53. Found 1-bit register for signal <bit_start>. Found 4-bit register for signal <bitcnt_reg>. Found 11-bit up counter for signal <count>. Found 1-bit register for signal <txd_reg>. Summary: inferred 1 Counter(s). inferred 6 D-type flip-flop(s). inferred 8 Latch(s). inferred 1 Adder/Subtracter(s). inferred 2 Comparator(s).Unit <send> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# Registers : 3 4-bit register : 1 1-bit register : 2# Latches : 1 8-bit latch : 1# Counters : 1 11-bit up counter : 1# Adders/Subtractors : 1 4-bit adder : 1# Comparators : 2 11-bit comparator less : 1 4-bit comparator less : 1=========================================================================Starting low level synthesis...Optimizing unit <send> ...=========================================================================Final ResultsOutput File Name : sendOutput Format : NGCOptimization Criterion : SpeedTarget Technology : 9500Keep Hierarchy : YESMacro Preserve : YESMacro Generation : AutoXOR Preserve : YESMacro Statistics# Comparators : 2 11-bit comparator less : 1 4-bit comparator less : 1# Xors : 13 1-bit xor2 : 13Design Statistics# Edif Instances : 147# I/Os : 10=========================================================================CPU : 2.25 / 2.41 s | Elapsed : 2.00 / 2.00 s --> EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.Done: completed successfully.
Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp send ngdbuild.rsp'
Creating TCL ProcessStarting: 'ngdbuild -f ngdbuild.rsp'Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc send.ucf -p XC9500 send.ngc send.ngd Reading NGO file "C:/WINDOWS/Desktop/send/send.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_10"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_10 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_3"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_4"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_4 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_5"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_5 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_6"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_6 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_7"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_7 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_8"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_8 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_9"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_9 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0017_Mxor_Result_1"...WARNING:LBEngine:353 - Module Madd__n0017_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0017_Mxor_Result_2"...WARNING:LBEngine:353 - Module Madd__n0017_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__n0017_Mxor_Result_3"...WARNING:LBEngine:353 - Module Madd__n0017_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Annotating constraints to design from file "send.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "send.ngd" ...Writing NGDBUILD log file "send.bld"...NGDBUILD done.Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.Done: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -tcl -command _cpldfit.tcl'
Creating TCL ProcessStarting: 'cpldfit -f _cpldfit.rsp send.ngd'Release 4.1WP3.x - X9K/XPLA Optimizer/Partitioner E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.WARNING:Cpld - Signal 'uart_buf_7.SETF' has been minimized to 'GND'. The signal is removed.WARNING:Cpld - Signal 'uart_buf_5.SETF' has been minimized to 'GND'. The signal is removed.WARNING:Cpld - Signal 'uart_buf_4.SETF' has been minimized to 'GND'. The signal is removed.Considering device XC95108-PC84.Flattening design..Multi-level logic optimization...Timing optimization........................................................WARNING:Cpld - Signal 'uart_buf_6.RSTF' has been minimized to 'GND'. The signal is removed.Timing driven global resource optimizationGeneral global resource optimization........Re-checking device resources ...Mapping a total of 33 equations into 6 function blocks.....Design send has been optimized and fit into device XC95108-7-PC84.Tcl _cpldfit.tcl detected that program 'cpldfit -f _cpldfit.rsp send.ngd' completed successfully.Done: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command hprep6 -i send -r int -a -l send.log -n send '
Starting: 'hprep6 -i send -r int -a -l send.log -n send 'Release 4.1WP3.x - Programming File Generator E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.EXEWRAP detected that program 'hprep6' completed successfully.Done: completed successfully.
Launching: 'impact -f __impact.rsp'
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