send.gyd

dp_xiliux 的 CPLD Verilog设计实验,串口演示.代码测试通过.

Pin Freeze File:  version E.33

9510884 XC95108-7-PC84
key_send<7> S:PIN63
key_send<0> S:PIN54
key_send<1> S:PIN55
key_send<2> S:PIN56
key_send<3> S:PIN57
key_send<4> S:PIN58
key_send<5> S:PIN61
key_send<6> S:PIN62
clock S:PIN9
txd S:PIN2


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.

PARTITION FB1_1 bitcnt_reg_2 EXP0_ txd_reg uart_buf_3
		 uart_buf_2 "uart_buf_1/uart_buf_1_SETF" "uart_buf_1/uart_buf_1_RSTF" "uart_buf_0/uart_buf_0_SETF"
		 bitcnt_reg_3 bitcnt_reg_1 "$OpTx$FX_DC$22" "$OpTx$FX_DC$21"
		 count_2 bitcnt_reg_0 "uart_buf_3/uart_buf_3_RSTF" EXP1_
		 "uart_buf_7/uart_buf_7_RSTF" "uart_buf_5/uart_buf_5_RSTF"
PARTITION FB2_3 uart_buf_6 uart_buf_5 uart_buf_4 count_9
		 count_8 count_10 count_0 bit_start
		 uart_buf_1 uart_buf_0 count_7 count_1
		 count_6 count_5 count_4 count_3
		
PARTITION FB3_18 uart_buf_7