__projnav.log

dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过.

ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_ledwater.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    ledwater.v
Writing ledwater.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Starting: 'exewrap @__filesAllClean_exewrap.rsp'


Creating TCL Process
Cleaning Up Project
deleting file(s): __projnav.log _impact.log
deleting file(s): tmperr.err automake.err
deleting file(s): ledwater.ngd
deleting file(s): __ledwater_2prj_exewrap.rsp _ngdbld.rsp ngdbuild.rsp __impact.rsp _cpldfit.rsp __filesAllClean_exewrap.rsp
deleting file(s): ledwater.ngc
deleting file(s): ledwater.prj
deleting file(s): ledwater.xst
deleting file(s): ledwater.syr
deleting file(s): ledwater._prj
deleting file(s): ledwater.bld
deleting file(s): ledwater_ngdbuild.nav
deleting directory: _ngo
deleting file(s): ledwater.jed
deleting file(s): ledwater.gyd
deleting file(s): ledwater.pnx
deleting file(s): ledwater.rpt
deleting file(s): ledwater.vm6
deleting file(s): _cpldfit.tcl
Finished cleaning up project

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Updating: Assign Pins (ChipViewer)

Starting: 'exewrap @__ledwater_2prj_exewrap.rsp'


Creating TCL Process
Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn ledwater.xst -ofn ledwater.syr'


Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn ledwater.xst -ofn ledwater.syr '


Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
CPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter overwrite set to YES
CPU : 0.00 / 0.16 s | Elapsed : 0.00 / 0.00 s
 
--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : ledwater.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : ledwater
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : ledwater
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : ledwater.prj
Compiling included source file 'ledwater.v'
Module <ledwater> compiled.
Continuing compilation of source file 'ledwater.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'ledwater.prj'
No errors in compilation
Analysis of file <ledwater.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <ledwater>.
WARNING:Xst:854 - "ledwater.v", line 7: Ignored initial statement.
Module <ledwater> is correct for synthesis.

Synthesizing Unit <ledwater>.
    Related source file is ledwater.v.
    Found 9-bit register for signal <ledout>.
    Found 22-bit adder for signal <$old_buffer_1>.
    Found 22-bit register for signal <buffer>.
    Summary:
	inferred  31 D-type flip-flop(s).
	inferred   1 Adder/Subtracter(s).
Unit <ledwater> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 2
  22-bit register                  : 1
  9-bit register                   : 1
# Adders/Subtractors               : 1
  22-bit adder                     : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <ledwater> ...
=========================================================================
Final Results
Output File Name                   : ledwater
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Xors                             : 21
  1-bit xor2                       : 21

Design Statistics
# Edif Instances                   : 129
# I/Os                             : 10

=========================================================================
CPU : 2.03 / 2.19 s | Elapsed : 2.00 / 2.00 s
 
--> 
EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.

Done: completed successfully.

Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp ledwater ngdbuild.rsp'


Creating TCL Process
Starting: 'ngdbuild -f ngdbuild.rsp'


Release 4.1WP3.x - ngdbuild E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.

Command Line: ngdbuild -dd _ngo -uc ledwater.ucf -p XC9500 ledwater.ngc
ledwater.ngd 

Reading NGO file "F:/    /Xilinx/ledwater/ledwater.ngc" ...
Reading component libraries for design expansion...
Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_1"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_1 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_10"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_10 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_11"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_11 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_12"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_12 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_13"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_13 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_14"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_14 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_15"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_15 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_16"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_16 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_17"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_17 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_18"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_18 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_19"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_19 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_2"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_2 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_20"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_20 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_21"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_21 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_3"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_3 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_Mxor_Result_4"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_4 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_5"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_5 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_6"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_6 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_7"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_7 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_8"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_8 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.Running LogiBLOX expansion on symbol "Madd__old_buffer_1_
Mxor_Result_9"...
WARNING:LBEngine:353 - Module Madd__old_buffer_1_Mxor_Result_9 : All styles for
   SIMPLE_GATES are implemented identically  for the XC9500 family.
Annotating constraints to design from file "ledwater.ucf" ...

Checking timing specifications ...

Checking expanded design ...

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   0

Writing NGD file "ledwater.ngd" ...

Writing NGDBUILD log file "ledwater.bld"...

NGDBUILD done.
Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.




Done: completed successfully.

Starting: 'exewrap -mode pipe -tapkeep -tcl -command _chipview.tcl'


Creating TCL Process
Starting: 'ChipView.bat -f ledwater.ngd -uc ledwater.ucf -dev XC95108-7-PC84'


Tcl _chipview.tcl detected that program 'ChipView.bat -f ledwater.ngd -uc ledwater.ucf -dev XC95108-7-PC84' completed successfully.




Starting: 'chkdate'


Tcl _chipview.tcl detected that program 'chkdate' completed successfully.

Existing implementation results (if any) will be retained.

Done: completed successfully.

ISE Auto-Make Log File
-----------------------

Starting: 'jhdparse @_ledwater.jp'


JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc.  All rights reserved. 

Scanning    d:/Xilinx_WebPACK/data/simprim.lst
Scanning    d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning    ledwater.v
Writing ledwater.jhd.

JHDPARSE complete -    0 errors,    0 warnings.

Done: completed successfully.

ISE Auto-Make Log File