ledwater.gyd

dp_xiliux 的 CPLD Verilog设计实验,流水灯演示.代码测试通过.

Pin Freeze File:  version E.33

9510884 XC95108-7-PC84
clk S:PIN9
ledout<1> S:PIN32
ledout<2> S:PIN33
ledout<3> S:PIN34
ledout<4> S:PIN35
ledout<5> S:PIN36
ledout<6> S:PIN37
ledout<7> S:PIN39
ledout<0> S:PIN31
ledout<8> S:PIN40


;The remaining section of the .gyd file is for documentation purposes only.
;It shows where your internal equations were placed in the last successful fit.



PARTITION FB3_4 buffer_9 buffer_8 buffer_7 buffer_6
		 buffer_5 buffer_4 buffer_3 buffer_2
		 buffer_13 buffer_12 buffer_11 buffer_10
		 buffer_1 n0000 buffer_0

PARTITION FB5_1 buffer_21 N116 N118 buffer_20
		 N120 N122 buffer_19 N124
		 N126 buffer_18 N128 "n0000$BUF0"
		 EXP0_ EXP1_ buffer_17 buffer_16
		 buffer_15 buffer_14