📄 clock.rpt
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(unused) 0 0 0 5 FB3_16 26 I/O
(unused) 0 0 0 5 FB3_17 31 I/O
(unused) 0 0 0 5 FB3_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB4 ***********************************
Number of function block inputs used/remaining: 0/36
Number of signals used by logic mapping into function block: 0
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 0 5 FB4_1 (b)
(unused) 0 0 0 5 FB4_2 57 I/O
(unused) 0 0 0 5 FB4_3 58 I/O
(unused) 0 0 0 5 FB4_4 (b)
(unused) 0 0 0 5 FB4_5 61 I/O
(unused) 0 0 0 5 FB4_6 62 I/O
(unused) 0 0 0 5 FB4_7 (b)
(unused) 0 0 0 5 FB4_8 63 I/O
(unused) 0 0 0 5 FB4_9 65 I/O
(unused) 0 0 0 5 FB4_10 (b)
(unused) 0 0 0 5 FB4_11 66 I/O
(unused) 0 0 0 5 FB4_12 67 I/O
(unused) 0 0 0 5 FB4_13 (b)
(unused) 0 0 0 5 FB4_14 68 I/O
(unused) 0 0 0 5 FB4_15 69 I/O
(unused) 0 0 0 5 FB4_16 (b)
(unused) 0 0 0 5 FB4_17 70 I/O
(unused) 0 0 0 5 FB4_18 (b)
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB5 ***********************************
Number of function block inputs used/remaining: 21/15
Number of signals used by logic mapping into function block: 21
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 /\5 0 FB5_1 (b) (b)
(unused) 0 0 /\5 0 FB5_2 32 I/O (b)
min_7 3 0 0 2 FB5_3 STD 33 I/O (b)
min_8 3 0 0 2 FB5_4 STD (b) (b)
min_4 3 0 0 2 FB5_5 STD 34 I/O (b)
min_6 4 0 0 1 FB5_6 STD 35 I/O (b)
min_5 5 0 0 0 FB5_7 STD (b) (b)
min_3 4 0 0 1 FB5_8 STD 36 I/O (b)
(unused) 0 0 \/5 0 FB5_9 37 I/O (b)
(unused) 0 0 \/5 0 FB5_10 (b) (b)
(unused) 0 0 \/5 0 FB5_11 39 I/O (b)
lddat<0> 16 15<- \/4 0 FB5_12 STD 40 I/O O
(unused) 0 0 \/5 0 FB5_13 (b) (b)
lddat<1> 16 11<- 0 0 FB5_14 STD 41 I/O O
lddat<2> 12 9<- /\2 0 FB5_15 STD 43 I/O O
(unused) 0 0 /\5 0 FB5_16 (b) (b)
lddat<3> 16 15<- /\4 0 FB5_17 STD 44 I/O O
(unused) 0 0 /\5 0 FB5_18 (b) (b)
Signals Used by Logic in Function Block
1: keyclr 8: min_11 15: min_4.FBK.LFBK
2: count_10 9: min_12 16: min_5.FBK.LFBK
3: count_11 10: min_13 17: min_6.FBK.LFBK
4: keyen_reg 11: min_14 18: min_7.FBK.LFBK
5: min_0 12: min_15 19: min_8.FBK.LFBK
6: min_1 13: min_2 20: min_9
7: min_10 14: min_3.FBK.LFBK 21: sec
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
min_7 X..XXX......XXXXXX..X................... 11 11
min_8 X..XXX......XXXXXXX.X................... 12 12
min_4 X..XXX......XXX.....X................... 8 8
min_6 X..XXX......XXXXXX..X................... 11 11
min_5 X..XXX......XXXXXX..X................... 11 11
min_3 X..XXX......XX......X................... 7 7
lddat<0> .XX.XXXXXXXXXXXXXXXX.................... 18 18
lddat<1> .XX.XXXXXXXXXXXXXXXX.................... 18 18
lddat<2> .XX.XXXXXXXXXXXXXXXX.................... 18 18
lddat<3> .XX.XXXXXXXXXXXXXXXX.................... 18 18
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB6 ***********************************
Number of function block inputs used/remaining: 22/14
Number of signals used by logic mapping into function block: 22
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
(unused) 0 0 \/5 0 FB6_1 (b) (b)
lddat<4> 12 7<- 0 0 FB6_2 STD 45 I/O O
lddat<5> 1 0 \/3 1 FB6_3 STD 46 I/O O
min_13 5 3<- \/3 0 FB6_4 STD (b) (b)
lddat<6> 12 7<- 0 0 FB6_5 STD 47 I/O O
lddat<7> 1 0 /\4 0 FB6_6 STD 48 I/O O
min_9 5 0 0 0 FB6_7 STD (b) (b)
ldsel<0> 1 0 0 4 FB6_8 STD 50 I/O O
ldsel<1> 1 0 0 4 FB6_9 STD 51 I/O O
min_11 4 0 0 1 FB6_10 STD (b) (b)
ldsel<2> 1 0 \/1 3 FB6_11 STD 52 I/O O
ldsel<3> 1 1<- \/5 0 FB6_12 STD 53 I/O O
lddat<5>_BUFR.MC 16 11<- 0 0 FB6_13 STD (b) (b)
(unused) 0 0 /\5 0 FB6_14 54 I/O I
min_14 4 0 /\1 0 FB6_15 STD 55 I/O I
min_10 3 0 0 2 FB6_16 STD (b) (b)
min_12 3 0 0 2 FB6_17 STD 56 I/O (b)
min_15 3 0 \/2 0 FB6_18 STD (b) (b)
Signals Used by Logic in Function Block
1: keyclr 9: min_11.FBK.LFBK 16: min_4
2: count_10 10: min_12.FBK.LFBK 17: min_5
3: count_11 11: min_13.FBK.LFBK 18: min_6
4: keyen_reg 12: min_14.FBK.LFBK 19: min_7
5: "lddat<5>_BUFR.FBK".LFBK
13: min_15.FBK.LFBK 20: min_8
6: min_0 14: min_2 21: min_9.FBK.LFBK
7: min_1 15: min_3 22: sec
8: min_10.FBK.LFBK
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
lddat<4> .XX..XXXXXXXXXXXXXXXX................... 18 18
lddat<5> ....X................................... 1 1
min_13 X..X.XXXXXXXXXXXXXXXXX.................. 19 19
lddat<6> .XX..XXXXXXXXXXXXXXXX................... 18 18
lddat<7> .XX..................X.................. 3 3
min_9 X..X.XXXX....XXXXXXXXX.................. 15 15
ldsel<0> .XX..................................... 2 2
ldsel<1> .XX..................................... 2 2
min_11 X..X.XXXX....XXXXXXXXX.................. 15 15
ldsel<2> .XX..................................... 2 2
ldsel<3> .XX..................................... 2 2
lddat<5>_BUFR.MC .XX..XXXXXXXXXXXXXXXX................... 18 18
min_14 X..X.XXXXXXXXXXXXXXXXX.................. 19 19
min_10 X..X.XXX.....XXXXXXXXX.................. 14 14
min_12 X..X.XXXXX...XXXXXXXXX.................. 16 16
min_15 X..X.XXXXXXXXXXXXXXXXX.................. 19 19
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK/FCLK - Global clock
O - Output GTS/FOE - Global 3state/output-enable
(b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.
"lddat<0>" = /count_10 * /count_11 * min_0 * min_1 * /min_2 *
min_3.FBK.LFBK
;Imported pterms FB5_11
+ count_10 * count_11 * min_12 * min_13 * /min_14 *
min_15
+ count_10 * count_11 * min_12 * /min_13 * min_14 *
min_15
+ /count_10 * /count_11 * min_0 * /min_1 * min_2 *
min_3.FBK.LFBK
+ /count_10 * /count_11 * min_0 * /min_1 * /min_2 *
/min_3.FBK.LFBK
+ /count_10 * /count_11 * /min_0 * /min_1 * min_2 *
/min_3.FBK.LFBK
;Imported pterms FB5_10
+ count_10 * count_11 * min_12 * /min_13 * /min_14 *
/min_15
+ count_10 * count_11 * /min_12 * /min_13 * min_14 *
/min_15
+ count_10 * /count_11 * min_4.FBK.LFBK *
min_6.FBK.LFBK * min_7.FBK.LFBK * /min_5.FBK.LFBK
+ count_10 * /count_11 * min_4.FBK.LFBK *
/min_6.FBK.LFBK * min_7.FBK.LFBK * min_5.FBK.LFBK
+ count_10 * /count_11 * min_4.FBK.LFBK *
/min_6.FBK.LFBK * /min_7.FBK.LFBK * /min_5.FBK.LFBK
;Imported pterms FB5_9
+ count_10 * /count_11 * /min_4.FBK.LFBK *
min_6.FBK.LFBK * /min_7.FBK.LFBK * /min_5.FBK.LFBK
+ /count_10 * count_11 * min_10 * /min_9 * min_11 *
min_8.FBK.LFBK
+ /count_10 * count_11 * min_10 * /min_9 * /min_11 *
/min_8.FBK.LFBK
+ /count_10 * count_11 * /min_10 * min_9 * min_11 *
min_8.FBK.LFBK
+ /count_10 * count_11 * /min_10 * /min_9 * /min_11 *
min_8.FBK.LFBK
"lddat<1>" = count_10 * count_11 * /min_12 * min_14 * min_15
+ count_10 * /count_11 * /min_4.FBK.LFBK *
min_6.FBK.LFBK * min_7.FBK.LFBK
+ /count_10 * count_11 * min_10 * min_11 *
/min_8.FBK.LFBK
+ /count_10 * /count_11 * /min_0 * min_1 * min_2
+ /count_10 * /count_11 * /min_0 * min_2 *
min_3.FBK.LFBK
;Imported pterms FB5_13
+ count_10 * count_11 * min_12 * min_13 * min_15
+ count_10 * count_11 * /min_12 * min_13 * min_14
+ count_10 * /count_11 * min_4.FBK.LFBK *
min_7.FBK.LFBK * min_5.FBK.LFBK
+ count_10 * /count_11 * /min_4.FBK.LFBK *
min_6.FBK.LFBK * min_5.FBK.LFBK
+ /count_10 * /count_11 * min_0 * min_1 *
min_3.FBK.LFBK
;Imported pterms FB5_12
+ count_10 * count_11 * min_12 * /min_13 * min_14 *
/min_15
+ count_10 * /count_11 * min_4.FBK.LFBK *
min_6.FBK.LFBK * /min_7.FBK.LFBK * /min_5.FBK.LFBK
+ /count_10 * count_11 * min_10 * /min_9 * /min_11 *
min_8.FBK.LFBK
+ /count_10 * /count_11 * min_0 * /min_1 * min_2 *
/min_3.FBK.LFBK
;Imported pterms FB5_15
+ /count_10 * count_11 * min_10 * min_9 *
/min_8.FBK.LFBK
+ /count_10 * count_11 * min_9 * min_11 *
min_8.FBK.LFBK
"lddat<2>" = count_10 * /count_11 * /min_4.FBK.LFBK *
min_6.FBK.LFBK * min_7.FBK.LFBK
+ /count_10 * count_11 * min_10 * min_11 *
/min_8.FBK.LFBK
+ /count_10 * /count_11 * /min_0 * min_2 *
min_3.FBK.LFBK
;Imported pterms FB5_16
+ count_10 * count_11 * /min_12 * min_14 * min_15
+ count_10 * count_11 * min_13 * min_14 * min_15
+ count_10 * /count_11 * min_6.FBK.LFBK *
min_7.FBK.LFBK * min_5.FBK.LFBK
+ /count_10 * count_11 * min_10 * min_9 * min_11
+ /count_10 * /count_11 * min_1 * min_2 *
min_3.FBK.LFBK
;Imported pterms FB5_17
+ count_10 * count_11 * /min_12 * min_13 * /min_14 *
/min_15
+ count_10 * /count_11 * /min_4.FBK.LFBK *
/min_6.FBK.LFBK * /min_7.FBK.LFBK * min_5.FBK.LFBK
+ /count_10 * count_11 * /min_10 * min_9 * /min_11 *
/min_8.FBK.LFBK
+ /count_10 * /count_11 * /min_0 * min_1 * /min_2 *
/min_3.FBK.LFBK
"lddat<3>" = /count_10 * count_11 * min_10 * min_9 *
min_8.FBK.LFBK
;Imported pterms FB5_18
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