sled.syr

来自「dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测」· SYR 代码 · 共 111 行

Release 4.1WP3.x - xst E.33
Copyright (c) 1995-2001 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to .
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--> Parameter overwrite set to YES
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--> =========================================================================
---- Source Parameters
Input Format                       : VERILOG
Input File Name                    : sled.prj

---- Target Parameters
Target Device                      : XC9500
Output File Name                   : sled
Output Format                      : NGC
Target Technology                  : 9500

---- Source Options
Top Module Name                    : sled
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Flip-Flop Type                 : D
Mux Extraction                     : YES
Resource Sharing                   : YES
Complex Clock Enable Extraction    : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
Macro Generator                    : Auto
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Criterion             : Speed
Optimization Effort                : 1
Check Attribute Syntax             : YES
Keep Hierarchy                     : YES

---- Other Options
wysiwyg                            : NO

=========================================================================

 
Compiling source file : sled.prj
Compiling included source file 'sled.v'
Module <sled> compiled.
Continuing compilation of source file 'sled.prj'
Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'
Continuing compilation of source file 'sled.prj'
No errors in compilation
Analysis of file <sled.prj> succeeded.
 
 
Starting Verilog synthesis.
 
Analyzing top module <sled>.
Module <sled> is correct for synthesis.

Synthesizing Unit <sled>.
    Related source file is sled.v.
WARNING:Xst:646 - Signal <sl_reg> is assigned but never used.
    Found 16x8-bit ROM for signal <seg_reg>.
    Found 37-bit up counter for signal <count>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
Unit <sled> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                             : 1
  16x8-bit ROM                     : 1
# Counters                         : 1
  37-bit up counter                : 1

=========================================================================


Starting low level synthesis...

Optimizing unit <sled> ...
=========================================================================
Final Results
Output File Name                   : sled
Output Format                      : NGC
Optimization Criterion             : Speed
Target Technology                  : 9500
Keep Hierarchy                     : YES
Macro Preserve                     : YES
Macro Generation                   : Auto
XOR Preserve                       : YES

Macro Statistics
# Xors                             : 36
  1-bit xor2                       : 36

Design Statistics
# Edif Instances                   : 163
# I/Os                             : 13

=========================================================================
CPU : 2.25 / 2.41 s | Elapsed : 3.00 / 3.00 s
 
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