📄 __projnav.log
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ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_dled.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning dled.v
Writing dled.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Updating: Assign Pins (ChipViewer)
Starting: 'exewrap @__dled_2prj_exewrap.rsp'
Creating TCL ProcessDone: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn dled.xst -ofn dled.syr'
Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn dled.xst -ofn dled.syr 'Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.22 s | Elapsed : 0.00 / 1.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.22 s | Elapsed : 0.00 / 1.00 s --> =========================================================================---- Source ParametersInput Format : VERILOGInput File Name : dled.prj---- Target ParametersTarget Device : XC9500Output File Name : dledOutput Format : NGCTarget Technology : 9500---- Source OptionsTop Module Name : dledAutomatic FSM Extraction : YESFSM Encoding Algorithm : AutoFSM Flip-Flop Type : DMux Extraction : YESResource Sharing : YESComplex Clock Enable Extraction : YES---- Target OptionsAdd IO Buffers : YESEquivalent register Removal : YESMacro Generator : AutoMACRO Preserve : YESXOR Preserve : YES---- General OptionsOptimization Criterion : SpeedOptimization Effort : 1Check Attribute Syntax : YESKeep Hierarchy : YES---- Other Optionswysiwyg : NO========================================================================= Compiling source file : dled.prjCompiling included source file 'dled.v'Module <dled> compiled.Continuing compilation of source file 'dled.prj'Compiling included source file 'd:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v'Continuing compilation of source file 'dled.prj'No errors in compilationAnalysis of file <dled.prj> succeeded. Starting Verilog synthesis. Analyzing top module <dled>.Module <dled> is correct for synthesis.Synthesizing Unit <dled>. Related source file is dled.v. Found 16x8-bit ROM for signal <seg_reg>. Found 37-bit up counter for signal <count>. Summary: inferred 1 ROM(s). inferred 1 Counter(s).Unit <dled> synthesized.=========================================================================HDL Synthesis ReportMacro Statistics# ROMs : 1 16x8-bit ROM : 1# Counters : 1 37-bit up counter : 1=========================================================================Starting low level synthesis...Optimizing unit <dled> ...=========================================================================Final ResultsOutput File Name : dledOutput Format : NGCOptimization Criterion : SpeedTarget Technology : 9500Keep Hierarchy : YESMacro Preserve : YESMacro Generation : AutoXOR Preserve : YESMacro Statistics# Xors : 36 1-bit xor2 : 36Design Statistics# Edif Instances : 163# I/Os : 13=========================================================================CPU : 2.31 / 2.53 s | Elapsed : 2.00 / 3.00 s --> EXEWRAP detected that program 'D:/Xilinx_WebPACK/bin/nt/xst.exe' completed successfully.Done: completed successfully.
Starting: 'exewrap -tapkeep -mode pipe -tcl -command d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl _ngdbld.rsp dled ngdbuild.rsp'
Creating TCL ProcessStarting: 'ngdbuild -f ngdbuild.rsp'Release 4.1WP3.x - ngdbuild E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.Command Line: ngdbuild -dd _ngo -uc dled.ucf -p XC9500 dled.ngc dled.ngd Reading NGO file "F:/ /Xilinx/7led/dled.ngc" ...Reading component libraries for design expansion...Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_1"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_1 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_10"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_10 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_11"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_11 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_12"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_12 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_13"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_13 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_14"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_14 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_15"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_15 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_16"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_16 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_17"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_17 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_18"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_18 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_19"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_19 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_2"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_2 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_20"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_20 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_21"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_21 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_22"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_22 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_23"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_23 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_24"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_24 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_25"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_25 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_26"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_26 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_27"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_27 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_28"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_28 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_29"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_29 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_3"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_3 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_30"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_30 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_31"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_31 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_32"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_32 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_33"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_33 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_34"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_34 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_35"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_35 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_36"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_36 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_4"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_4 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_5"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_5 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_6"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_6 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_7"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_7 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_8"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_8 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Running LogiBLOX expansion on symbol "count_Madd__n0000_Mxor_Result_9"...WARNING:LBEngine:353 - Module count_Madd__n0000_Mxor_Result_9 : All styles for SIMPLE_GATES are implemented identically for the XC9500 family.Annotating constraints to design from file "dled.ucf" ...Checking timing specifications ...Checking expanded design ...NGDBUILD Design Results Summary: Number of errors: 0 Number of warnings: 0Writing NGD file "dled.ngd" ...Writing NGDBUILD log file "dled.bld"...NGDBUILD done.Tcl d:/Xilinx_WebPACK/data/projnav/_edfTOngd.tcl detected that program 'ngdbuild -f ngdbuild.rsp' completed successfully.Done: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -tcl -command _chipview.tcl'
Creating TCL ProcessStarting: 'ChipView.bat -f dled.ngd -uc dled.ucf -dev XC95108-7-PC84'Tcl _chipview.tcl detected that program 'ChipView.bat -f dled.ngd -uc dled.ucf -dev XC95108-7-PC84' completed successfully.Starting: 'chkdate'Tcl _chipview.tcl detected that program 'chkdate' completed successfully.Existing implementation results (if any) will be retained.Done: completed successfully.
ISE Auto-Make Log File-----------------------
Starting: 'jhdparse @_dled.jp'
JHDPARSE - VHDL/Verilog Parser.
ISE 4.1i Copyright(c) 1999-2001 Xilinx, Inc. All rights reserved.
Scanning d:/Xilinx_WebPACK/data/simprim.lst
Scanning d:/Xilinx_WebPACK/verilog/src/iSE/unisim_comp.v
Scanning dled.v
Writing dled.jhd.
JHDPARSE complete - 0 errors, 0 warnings.
Done: completed successfully.
ISE Auto-Make Log File-----------------------
Updating: Configure Device (iMPACT)
Starting: 'exewrap @__dled_2prj_exewrap.rsp'
Creating TCL ProcessDone: completed successfully.
Starting: 'exewrap -mode pipe -tapkeep -command D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn dled.xst -ofn dled.syr'
Starting: 'D:/Xilinx_WebPACK/bin/nt/xst.exe -ifn dled.xst -ofn dled.syr 'Release 4.1WP3.x - xst E.33Copyright (c) 1995-2001 Xilinx, Inc. All rights reserved.--> Parameter TMPDIR set to .CPU : 0.00 / 0.17 s | Elapsed : 0.00 / 0.00 s --> Parameter overwrite set to YESCPU : 0.00 / 0.17 s | Elapsed : 0.00 / 0.00 s --> =========================================================================---- Source ParametersInput Format : VERILOGInput File Name : dled.prj---- Target ParametersTarget Device : XC9500Output File Name : dledOutput Format : NGCTarget Technology : 9500---- Source OptionsTop Module Name : dledAutomatic FSM Extraction : YESFSM Encoding Algorithm : Auto⌨️ 快捷键说明
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