last_used.ucf

dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过.

// Template UCF file created by the Project Navigator
NET clock LOC=P9;
NET seg<0> LOC=P40;
NET seg<1> LOC=P41;
NET seg<2> LOC=P43;
NET seg<3> LOC=P44;
NET seg<4> LOC=P45;
NET seg<5> LOC=P46;
NET seg<6> LOC=P47;
NET seg<7> LOC=P48;
NET sl<0> LOC=P50;
NET sl<1> LOC=P51;
NET sl<2> LOC=P52;
NET sl<3> LOC=P53;