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📄 dled.rpt

📁 dp_xiliux 的 CPLD Verilog设计实验,7个LED演示.代码测试通过.
💻 RPT
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cpldfit:  version E.33                              Xilinx Inc.
                                  Fitter Report
Design Name: dled                                Date: 11-19-2002, 10:42AM
Device Used: XC95108-7-PC84
Fitting Status: Successful

****************************  Resource Summary  ****************************

Macrocells     Product Terms    Registers      Pins           Function Block 
Used           Used             Used           Used           Inputs Used    
27 /108 ( 25%) 27  /540  (  5%) 15 /108 ( 13%) 13 /69  ( 18%) 19 /216 (  8%)

PIN RESOURCES:

Signal Type    Required     Mapped  |  Pin Type            Used   Remaining 
------------------------------------|---------------------------------------
Input         :    0           0    |  I/O              :    12       51
Output        :   12          12    |  GCK/IO           :     1        2
Bidirectional :    0           0    |  GTS/IO           :     0        2
GCK           :    1           1    |  GSR/IO           :     0        1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     13          13

MACROCELL RESOURCES:

Total Macrocells Available                   108
Registered Macrocells                         15
Non-registered Macrocell driving I/O          12

GLOBAL RESOURCES:

Signal 'clock' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

POWER DATA:

There are 27 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 27 macrocells used (MC).

End of Resource Summary
***************Resources Used by Successfully Mapped Logic******************

** LOGIC **
Signal              Total   Signals Loc     Pwr  Slew Pin  Pin       Pin
Name                Pt      Used            Mode Rate #    Type      Use
count_0             1       1       FB6_18  STD            (b)       (b)
count_1             1       1       FB6_17  STD       56   I/O       (b)
count_10            1       10      FB5_18  STD            (b)       (b)
count_11            1       11      FB5_16  STD            (b)       (b)
count_12            1       12      FB5_13  STD            (b)       (b)
count_13            1       13      FB5_11  STD       39   I/O       (b)
count_14            1       14      FB5_10  STD            (b)       (b)
count_2             1       2       FB6_16  STD            (b)       (b)
count_3             1       3       FB5_9   STD       37   I/O       (b)
count_4             1       4       FB5_8   STD       36   I/O       (b)
count_5             1       5       FB5_7   STD            (b)       (b)
count_6             1       6       FB5_6   STD       35   I/O       (b)
count_7             1       7       FB5_5   STD       34   I/O       (b)
count_8             1       8       FB5_4   STD            (b)       (b)
count_9             1       9       FB5_3   STD       33   I/O       (b)
seg<0>              2       2       FB5_12  STD  FAST 40   I/O       O
seg<1>              0       0       FB5_14  STD  FAST 41   I/O       O
seg<2>              1       2       FB5_15  STD  FAST 43   I/O       O
seg<3>              2       2       FB5_17  STD  FAST 44   I/O       O
seg<4>              1       2       FB6_2   STD  FAST 45   I/O       O
seg<5>              1       2       FB6_3   STD  FAST 46   I/O       O
seg<6>              1       2       FB6_5   STD  FAST 47   I/O       O
seg<7>              0       0       FB6_6   STD  FAST 48   I/O       O
sl<0>               1       2       FB6_8   STD  FAST 50   I/O       O
sl<1>               1       2       FB6_9   STD  FAST 51   I/O       O
sl<2>               1       2       FB6_11  STD  FAST 52   I/O       O
sl<3>               1       2       FB6_12  STD  FAST 53   I/O       O

** INPUTS **
Signal                              Loc               Pin  Pin       Pin
Name                                                  #    Type      Use
clock                               FB1_12            9    GCK/I/O   GCK

End of Resources Used by Successfully Mapped Logic

*********************Function Block Resource Summary***********************
Function    # of        FB Inputs   Signals     Total       O/IO      IO    
Block       Macrocells  Used        Used        Pt Used     Req       Avail 
FB1           0           0           0            0         0/0       12   
FB2           0           0           0            0         0/0       12   
FB3           0           0           0            0         0/0       12   
FB4           0           0           0            0         0/0       11   
FB5          16          15          15           17         4/0       11   
FB6          11           4           4           10         8/0       11   
            ----                                -----       -----     ----- 
             27                                   27        12/0       69   
*********************************** FB1 ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB1_1               (b)     
(unused)              0       0     0   5     FB1_2         1     I/O     
(unused)              0       0     0   5     FB1_3         2     I/O     
(unused)              0       0     0   5     FB1_4               (b)     
(unused)              0       0     0   5     FB1_5         3     I/O     
(unused)              0       0     0   5     FB1_6         4     I/O     
(unused)              0       0     0   5     FB1_7               (b)     
(unused)              0       0     0   5     FB1_8         5     I/O     
(unused)              0       0     0   5     FB1_9         6     I/O     
(unused)              0       0     0   5     FB1_10              (b)     
(unused)              0       0     0   5     FB1_11        7     I/O     
(unused)              0       0     0   5     FB1_12        9     GCK/I/O GCK
(unused)              0       0     0   5     FB1_13              (b)     
(unused)              0       0     0   5     FB1_14        10    GCK/I/O 
(unused)              0       0     0   5     FB1_15        11    I/O     
(unused)              0       0     0   5     FB1_16        12    GCK/I/O 
(unused)              0       0     0   5     FB1_17        13    I/O     
(unused)              0       0     0   5     FB1_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB2_1               (b)     
(unused)              0       0     0   5     FB2_2         71    I/O     
(unused)              0       0     0   5     FB2_3         72    I/O     
(unused)              0       0     0   5     FB2_4               (b)     
(unused)              0       0     0   5     FB2_5         74    GSR/I/O 
(unused)              0       0     0   5     FB2_6         75    I/O     
(unused)              0       0     0   5     FB2_7               (b)     
(unused)              0       0     0   5     FB2_8         76    GTS/I/O 
(unused)              0       0     0   5     FB2_9         77    GTS/I/O 
(unused)              0       0     0   5     FB2_10              (b)     
(unused)              0       0     0   5     FB2_11        79    I/O     
(unused)              0       0     0   5     FB2_12        80    I/O     
(unused)              0       0     0   5     FB2_13              (b)     
(unused)              0       0     0   5     FB2_14        81    I/O     
(unused)              0       0     0   5     FB2_15        82    I/O     
(unused)              0       0     0   5     FB2_16        83    I/O     
(unused)              0       0     0   5     FB2_17        84    I/O     
(unused)              0       0     0   5     FB2_18              (b)     
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input            GCK/FCLK - Global clock
               O  - Output           GTS/FOE  - Global 3state/output-enable
              (b) - Buried macrocell
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
*********************************** FB3 ***********************************
Number of function block inputs used/remaining:               0/36
Number of signals used by logic mapping into function block:  0
Signal              Total   Imp   Exp Unused  Loc     Pwr   Pin   Pin     Pin
Name                Pt      Pt    Pt  Pt              Mode   #    Type    Use
(unused)              0       0     0   5     FB3_1               (b)     
(unused)              0       0     0   5     FB3_2         14    I/O     
(unused)              0       0     0   5     FB3_3         15    I/O     
(unused)              0       0     0   5     FB3_4               (b)     
(unused)              0       0     0   5     FB3_5         17    I/O     
(unused)              0       0     0   5     FB3_6         18    I/O     
(unused)              0       0     0   5     FB3_7               (b)     
(unused)              0       0     0   5     FB3_8         19    I/O     
(unused)              0       0     0   5     FB3_9         20    I/O     
(unused)              0       0     0   5     FB3_10              (b)     
(unused)              0       0     0   5     FB3_11        21    I/O     

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