dds_vhdl.map.eqn

基于fpga的正弦波发生器设计

U1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[2], U1_ram_rom_data_reg[3], T1_q_b[2], U1L01, VCC, U1L9);


--U1_ram_rom_data_reg[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1]
--operation mode is normal

U1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[1], U1_ram_rom_data_reg[2], T1_q_b[1], U1L01, VCC, U1L9);


--U1_ram_rom_data_reg[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0]
--operation mode is normal

U1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[0], U1_ram_rom_data_reg[1], T1_q_b[0], U1L01, VCC, U1L9);


--B1L51Q is sld_hub:sld_hub_inst|HUB_TDO~reg0
--operation mode is normal

B1L51Q = AMPP_FUNCTION(!A1L5, B1_jtag_debug_mode_usr1, K6_Q[0], B1L31, B1L11, !P1_state[8], B1L92);


--X1_safe_q[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[1]
--operation mode is arithmetic

X1_safe_q[1] = AMPP_FUNCTION(A1L5, X1_safe_q[1], U1L01, !K1_Q[3], U1L83, X1L2);

--X1L4 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

X1L4 = AMPP_FUNCTION(X1_safe_q[1], X1L2);


--X1_safe_q[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[2]
--operation mode is arithmetic

X1_safe_q[2] = AMPP_FUNCTION(A1L5, X1_safe_q[2], U1L01, !K1_Q[3], U1L83, X1L4);

--X1L6 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

X1L6 = AMPP_FUNCTION(X1_safe_q[2], X1L4);


--X1_safe_q[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[0]
--operation mode is arithmetic

X1_safe_q[0] = AMPP_FUNCTION(A1L5, X1_safe_q[0], U1L01, !K1_Q[3], U1L83);

--X1L2 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

X1L2 = AMPP_FUNCTION(X1_safe_q[0]);


--X1_safe_q[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[3]
--operation mode is normal

X1_safe_q[3] = AMPP_FUNCTION(A1L5, X1_safe_q[3], U1L01, !K1_Q[3], U1L83, X1L6);


--U1L83 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_load_read_data~17
--operation mode is normal

U1L83 = AMPP_FUNCTION(X1_safe_q[1], X1_safe_q[2], X1_safe_q[0], X1_safe_q[3]);


--K2_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2]
--operation mode is normal

K2_Q[2] = AMPP_FUNCTION(A1L5, K6_Q[2], !B1L2, B1L8);


--K6_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2]
--operation mode is normal

K6_Q[2] = AMPP_FUNCTION(A1L5, K6_Q[2], U1_ir_loaded_address_reg[1], K6_Q[3], B1L61, !B1L2, P1_state[4], B1_IRSR_ENA);


--K3_Q[0] is sld_hub:sld_hub_inst|sld_dffex:BROADCAST|Q[0]
--operation mode is normal

K3_Q[0] = AMPP_FUNCTION(A1L5, Q1_dffe1a[1], !B1L2, B1L1);


--K7_Q[0] is sld_hub:sld_hub_inst|sld_dffex:RESET|Q[0]
--operation mode is normal

K7_Q[0] = AMPP_FUNCTION(A1L5, Q1_dffe1a[7], B1_jtag_debug_mode_usr1, B1L3);


--P1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1]
--operation mode is normal

P1_state[1] = AMPP_FUNCTION(A1L5, P1_state[0], P1L81, A1L7, VCC);


--B1L2 is sld_hub:sld_hub_inst|CLEAR_SIGNAL~0
--operation mode is normal

B1L2 = AMPP_FUNCTION(K7_Q[0], P1_state[1]);


--K5_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA_0|Q[0]
--operation mode is normal

K5_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, VCC, B1L71);


--Q1_dffe1a[2] is sld_hub:sld_hub_inst|lpm_decode:instruction_decoder|decode_9ie:auto_generated|dffe1a[2]
--operation mode is normal

Q1_dffe1a[2] = AMPP_FUNCTION(A1L5, K6_Q[2], B1L42, K6_Q[3], K6_Q[1], !B1L2, B1L7);


--K4_Q[0] is sld_hub:sld_hub_inst|sld_dffex:IRF_ENA|Q[0]
--operation mode is normal

K4_Q[0] = AMPP_FUNCTION(A1L5, altera_internal_jtag, !B1L2, B1L71);


--B1L81 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~76
--operation mode is normal

B1L81 = AMPP_FUNCTION(K5_Q[0], Q1_dffe1a[2], K4_Q[0], K3_Q[0]);


--P1_state[5] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[5]
--operation mode is normal

P1_state[5] = AMPP_FUNCTION(A1L5, A1L7, P1_state[4], P1_state[3], VCC);


--B1_OK_TO_UPDATE_IR_Q is sld_hub:sld_hub_inst|OK_TO_UPDATE_IR_Q
--operation mode is normal

B1_OK_TO_UPDATE_IR_Q = AMPP_FUNCTION(A1L5, B1_jtag_debug_mode_usr1, P1_state[8], VCC, B1L82);


--B1L91 is sld_hub:sld_hub_inst|IRF_ENABLE[1]~77
--operation mode is normal

B1L91 = AMPP_FUNCTION(B1L81, P1_state[5], B1_OK_TO_UPDATE_IR_Q);


--D1_dout[22] is reg32b:u2|dout[22]
--operation mode is arithmetic

D1_dout[22]_carry_eqn = D1L33;
D1_dout[22]_lut_out = D1_dout[22] $ !D1_dout[22]_carry_eqn;
D1_dout[22] = DFFEA(D1_dout[22]_lut_out, J1_clock0, Y1__locked, , , , );

--D1L53 is reg32b:u2|dout[22]~COUT
--operation mode is arithmetic

D1L53 = CARRY(D1_dout[22] & !D1L33);


--D1_dout[23] is reg32b:u2|dout[23]
--operation mode is arithmetic

D1_dout[23]_carry_eqn = D1L53;
D1_dout[23]_lut_out = D1_dout[23] $ D1_dout[23]_carry_eqn;
D1_dout[23] = DFFEA(D1_dout[23]_lut_out, J1_clock0, Y1__locked, , , , );

--D1L73 is reg32b:u2|dout[23]~COUT
--operation mode is arithmetic

D1L73 = CARRY(!D1L53 # !D1_dout[23]);


--D1_dout[24] is reg32b:u2|dout[24]
--operation mode is arithmetic

D1_dout[24]_carry_eqn = D1L73;
D1_dout[24]_lut_out = D1_dout[24] $ !D1_dout[24]_carry_eqn;
D1_dout[24] = DFFEA(D1_dout[24]_lut_out, J1_clock0, Y1__locked, , , , );

--D1L93 is reg32b:u2|dout[24]~COUT
--operation mode is arithmetic

D1L93 = CARRY(D1_dout[24] & !D1L73);


--D1_dout[25] is reg32b:u2|dout[25]
--operation mode is arithmetic

D1_dout[25]_carry_eqn = D1L93;
D1_dout[25]_lut_out = D1_dout[25] $ D1_dout[25]_carry_eqn;
D1_dout[25] = DFFEA(D1_dout[25]_lut_out, J1_clock0, Y1__locked, , , , );

--D1L14 is reg32b:u2|dout[25]~COUT
--operation mode is arithmetic

D1L14 = CARRY(!D1L93 # !D1_dout[25]);


--D1_dout[26] is reg32b:u2|dout[26]
--operation mode is arithmetic

D1_dout[26]_carry_eqn = D1L14;
D1_dout[26]_lut_out = D1_dout[26] $ !D1_dout[26]_carry_eqn;
D1_dout[26] = DFFEA(D1_dout[26]_lut_out, J1_clock0, Y1__locked, , , , );

--D1L34 is reg32b:u2|dout[26]~COUT
--operation mode is arithmetic

D1L34 = CARRY(D1_dout[26] & !D1L14);


--D1_dout[27] is reg32b:u2|dout[27]
--operation mode is arithmetic

D1_dout[27]_carry_eqn = D1L34;
D1_dout[27]_lut_out = D1_dout[27] $ D1_dout[27]_carry_eqn;
D1_dout[27] = DFFEA(D1_dout[27]_lut_out, J1_clock0, Y1__locked, , , , );

--D1L54 is reg32b:u2|dout[27]~COUT
--operation mode is arithmetic

D1L54 = CARRY(!D1L34 # !D1_dout[27]);


--D1_dout[28] is reg32b:u2|dout[28]
--operation mode is arithmetic

D1_dout[28]_carry_eqn = D1L54;
D1_dout[28]_lut_out = D1_dout[28] $ !D1_dout[28]_carry_eqn;
D1_dout[28] = DFFEA(D1_dout[28]_lut_out, J1_clock0, Y1__locked, , , , );

--D1L74 is reg32b:u2|dout[28]~COUT
--operation mode is arithmetic

D1L74 = CARRY(D1_dout[28] & !D1L54);


--D1_dout[29] is reg32b:u2|dout[29]
--operation mode is arithmetic

D1_dout[29]_carry_eqn = D1L74;
D1_dout[29]_lut_out = D1_dout[29] $ D1_dout[29]_carry_eqn;
D1_dout[29] = DFFEA(D1_dout[29]_lut_out, J1_clock0, Y1__locked, , , , );

--D1L94 is reg32b:u2|dout[29]~COUT
--operation mode is arithmetic

D1L94 = CARRY(!D1L74 # !D1_dout[29]);