dds_vhdl.map.eqn

基于fpga的正弦波发生器设计

G1_dout[2]_carry_eqn = G1L5;
G1_dout[2]_lut_out = D1_dout[24] $ pword[2] $ !G1_dout[2]_carry_eqn;
G1_dout[2] = DFFEA(G1_dout[2]_lut_out, J1_clock0, Y1__locked, , , , );

--G1L7 is reg10b:u5|dout[2]~COUT
--operation mode is arithmetic

G1L7 = CARRY(D1_dout[24] & (pword[2] # !G1L5) # !D1_dout[24] & pword[2] & !G1L5);


--G1_dout[3] is reg10b:u5|dout[3]
--operation mode is arithmetic

G1_dout[3]_carry_eqn = G1L7;
G1_dout[3]_lut_out = D1_dout[25] $ pword[3] $ G1_dout[3]_carry_eqn;
G1_dout[3] = DFFEA(G1_dout[3]_lut_out, J1_clock0, Y1__locked, , , , );

--G1L9 is reg10b:u5|dout[3]~COUT
--operation mode is arithmetic

G1L9 = CARRY(D1_dout[25] & !pword[3] & !G1L7 # !D1_dout[25] & (!G1L7 # !pword[3]));


--G1_dout[4] is reg10b:u5|dout[4]
--operation mode is arithmetic

G1_dout[4]_carry_eqn = G1L9;
G1_dout[4]_lut_out = D1_dout[26] $ pword[4] $ !G1_dout[4]_carry_eqn;
G1_dout[4] = DFFEA(G1_dout[4]_lut_out, J1_clock0, Y1__locked, , , , );

--G1L11 is reg10b:u5|dout[4]~COUT
--operation mode is arithmetic

G1L11 = CARRY(D1_dout[26] & (pword[4] # !G1L9) # !D1_dout[26] & pword[4] & !G1L9);


--G1_dout[5] is reg10b:u5|dout[5]
--operation mode is arithmetic

G1_dout[5]_carry_eqn = G1L11;
G1_dout[5]_lut_out = D1_dout[27] $ pword[5] $ G1_dout[5]_carry_eqn;
G1_dout[5] = DFFEA(G1_dout[5]_lut_out, J1_clock0, Y1__locked, , , , );

--G1L31 is reg10b:u5|dout[5]~COUT
--operation mode is arithmetic

G1L31 = CARRY(D1_dout[27] & !pword[5] & !G1L11 # !D1_dout[27] & (!G1L11 # !pword[5]));


--G1_dout[6] is reg10b:u5|dout[6]
--operation mode is arithmetic

G1_dout[6]_carry_eqn = G1L31;
G1_dout[6]_lut_out = D1_dout[28] $ pword[6] $ !G1_dout[6]_carry_eqn;
G1_dout[6] = DFFEA(G1_dout[6]_lut_out, J1_clock0, Y1__locked, , , , );

--G1L51 is reg10b:u5|dout[6]~COUT
--operation mode is arithmetic

G1L51 = CARRY(D1_dout[28] & (pword[6] # !G1L31) # !D1_dout[28] & pword[6] & !G1L31);


--G1_dout[7] is reg10b:u5|dout[7]
--operation mode is arithmetic

G1_dout[7]_carry_eqn = G1L51;
G1_dout[7]_lut_out = D1_dout[29] $ pword[7] $ G1_dout[7]_carry_eqn;
G1_dout[7] = DFFEA(G1_dout[7]_lut_out, J1_clock0, Y1__locked, , , , );

--G1L71 is reg10b:u5|dout[7]~COUT
--operation mode is arithmetic

G1L71 = CARRY(D1_dout[29] & !pword[7] & !G1L51 # !D1_dout[29] & (!G1L51 # !pword[7]));


--G1_dout[8] is reg10b:u5|dout[8]
--operation mode is arithmetic

G1_dout[8]_carry_eqn = G1L71;
G1_dout[8]_lut_out = D1_dout[30] $ !G1_dout[8]_carry_eqn;
G1_dout[8] = DFFEA(G1_dout[8]_lut_out, J1_clock0, Y1__locked, , , , );

--G1L91 is reg10b:u5|dout[8]~COUT
--operation mode is arithmetic

G1L91 = CARRY(D1_dout[30] & !G1L71);


--G1_dout[9] is reg10b:u5|dout[9]
--operation mode is normal

G1_dout[9]_carry_eqn = G1L91;
G1_dout[9]_lut_out = D1_dout[31] $ G1_dout[9]_carry_eqn;
G1_dout[9] = DFFEA(G1_dout[9]_lut_out, J1_clock0, Y1__locked, , , , );


--U1_ram_rom_data_reg[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[9]
--operation mode is normal

U1_ram_rom_data_reg[9] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[9], altera_internal_jtag, T1_q_b[9], U1L01, VCC, U1L9);


--W1_safe_q[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[0]
--operation mode is arithmetic

W1_safe_q[0] = AMPP_FUNCTION(A1L5, W1_safe_q[0], U1L31, !K1_Q[0], U1_ram_rom_incr_addr);

--W1L2 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella0~COUT
--operation mode is arithmetic

W1L2 = AMPP_FUNCTION(W1_safe_q[0]);


--W1_safe_q[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[1]
--operation mode is arithmetic

W1_safe_q[1] = AMPP_FUNCTION(A1L5, W1_safe_q[1], U1L41, !K1_Q[0], U1_ram_rom_incr_addr, W1L2);

--W1L4 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella1~COUT
--operation mode is arithmetic

W1L4 = AMPP_FUNCTION(W1_safe_q[1], W1L2);


--W1_safe_q[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[2]
--operation mode is arithmetic

W1_safe_q[2] = AMPP_FUNCTION(A1L5, W1_safe_q[2], U1L51, !K1_Q[0], U1_ram_rom_incr_addr, W1L4);

--W1L6 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella2~COUT
--operation mode is arithmetic

W1L6 = AMPP_FUNCTION(W1_safe_q[2], W1L4);


--W1_safe_q[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[3]
--operation mode is arithmetic

W1_safe_q[3] = AMPP_FUNCTION(A1L5, W1_safe_q[3], U1L61, !K1_Q[0], U1_ram_rom_incr_addr, W1L6);

--W1L8 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella3~COUT
--operation mode is arithmetic

W1L8 = AMPP_FUNCTION(W1_safe_q[3], W1L6);


--W1_safe_q[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[4]
--operation mode is arithmetic

W1_safe_q[4] = AMPP_FUNCTION(A1L5, W1_safe_q[4], U1L71, !K1_Q[0], U1_ram_rom_incr_addr, W1L8);

--W1L01 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella4~COUT
--operation mode is arithmetic

W1L01 = AMPP_FUNCTION(W1_safe_q[4], W1L8);


--W1_safe_q[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[5]
--operation mode is arithmetic

W1_safe_q[5] = AMPP_FUNCTION(A1L5, W1_safe_q[5], U1L81, !K1_Q[0], U1_ram_rom_incr_addr, W1L01);

--W1L21 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella5~COUT
--operation mode is arithmetic

W1L21 = AMPP_FUNCTION(W1_safe_q[5], W1L01);


--W1_safe_q[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[6]
--operation mode is arithmetic

W1_safe_q[6] = AMPP_FUNCTION(A1L5, W1_safe_q[6], U1L91, !K1_Q[0], U1_ram_rom_incr_addr, W1L21);

--W1L41 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella6~COUT
--operation mode is arithmetic

W1L41 = AMPP_FUNCTION(W1_safe_q[6], W1L21);


--W1_safe_q[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[7]
--operation mode is arithmetic

W1_safe_q[7] = AMPP_FUNCTION(A1L5, W1_safe_q[7], U1L02, !K1_Q[0], U1_ram_rom_incr_addr, W1L41);

--W1L61 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella7~COUT
--operation mode is arithmetic

W1L61 = AMPP_FUNCTION(W1_safe_q[7], W1L41);


--W1_safe_q[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[8]
--operation mode is arithmetic

W1_safe_q[8] = AMPP_FUNCTION(A1L5, W1_safe_q[8], U1L12, !K1_Q[0], U1_ram_rom_incr_addr, W1L61);

--W1L81 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella8~COUT
--operation mode is arithmetic

W1L81 = AMPP_FUNCTION(W1_safe_q[8], W1L61);


--W1_safe_q[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[9]
--operation mode is normal

W1_safe_q[9] = AMPP_FUNCTION(A1L5, W1_safe_q[9], U1L22, !K1_Q[0], U1_ram_rom_incr_addr, W1L81);


--U1_ram_rom_data_reg[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[8]
--operation mode is normal

U1_ram_rom_data_reg[8] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[8], U1_ram_rom_data_reg[9], T1_q_b[8], U1L01, VCC, U1L9);


--U1_ram_rom_data_reg[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7]
--operation mode is normal

U1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[7], U1_ram_rom_data_reg[8], T1_q_b[7], U1L01, VCC, U1L9);


--U1_ram_rom_data_reg[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]
--operation mode is normal

U1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[6], U1_ram_rom_data_reg[7], T1_q_b[6], U1L01, VCC, U1L9);


--U1_ram_rom_data_reg[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5]
--operation mode is normal

U1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[5], U1_ram_rom_data_reg[6], T1_q_b[5], U1L01, VCC, U1L9);


--U1_ram_rom_data_reg[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4]
--operation mode is normal

U1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[4], U1_ram_rom_data_reg[5], T1_q_b[4], U1L01, VCC, U1L9);


--U1_ram_rom_data_reg[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3]
--operation mode is normal

U1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[3], U1_ram_rom_data_reg[4], T1_q_b[3], U1L01, VCC, U1L9);


--U1_ram_rom_data_reg[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2]
--operation mode is normal