dds_vhdl.map.eqn

基于fpga的正弦波发生器设计

--T1_q_b[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[4]
T1_q_b[4]_PORT_A_data_in = VCC;
T1_q_b[4]_PORT_A_data_in_reg = DFFE(T1_q_b[4]_PORT_A_data_in, T1_q_b[4]_clock_0, , , );
T1_q_b[4]_PORT_B_data_in = U1_ram_rom_data_reg[4];
T1_q_b[4]_PORT_B_data_in_reg = DFFE(T1_q_b[4]_PORT_B_data_in, T1_q_b[4]_clock_1, , , );
T1_q_b[4]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[4]_PORT_A_address_reg = DFFE(T1_q_b[4]_PORT_A_address, T1_q_b[4]_clock_0, , , );
T1_q_b[4]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[4]_PORT_B_address_reg = DFFE(T1_q_b[4]_PORT_B_address, T1_q_b[4]_clock_1, , , );
T1_q_b[4]_PORT_A_write_enable = GND;
T1_q_b[4]_PORT_A_write_enable_reg = DFFE(T1_q_b[4]_PORT_A_write_enable, T1_q_b[4]_clock_0, , , );
T1_q_b[4]_PORT_B_write_enable = U1L53;
T1_q_b[4]_PORT_B_write_enable_reg = DFFE(T1_q_b[4]_PORT_B_write_enable, T1_q_b[4]_clock_1, , , );
T1_q_b[4]_clock_0 = J1_clock0;
T1_q_b[4]_clock_1 = A1L5;
T1_q_b[4]_PORT_B_data_out = MEMORY(T1_q_b[4]_PORT_A_data_in_reg, T1_q_b[4]_PORT_B_data_in_reg, T1_q_b[4]_PORT_A_address_reg, T1_q_b[4]_PORT_B_address_reg, T1_q_b[4]_PORT_A_write_enable_reg, T1_q_b[4]_PORT_B_write_enable_reg, , , T1_q_b[4]_clock_0, T1_q_b[4]_clock_1, , , , );
T1_q_b[4] = T1_q_b[4]_PORT_B_data_out[0];


--T1_q_a[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[3]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[3]_PORT_A_data_in = VCC;
T1_q_a[3]_PORT_A_data_in_reg = DFFE(T1_q_a[3]_PORT_A_data_in, T1_q_a[3]_clock_0, , , );
T1_q_a[3]_PORT_B_data_in = U1_ram_rom_data_reg[3];
T1_q_a[3]_PORT_B_data_in_reg = DFFE(T1_q_a[3]_PORT_B_data_in, T1_q_a[3]_clock_1, , , );
T1_q_a[3]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[3]_PORT_A_address_reg = DFFE(T1_q_a[3]_PORT_A_address, T1_q_a[3]_clock_0, , , );
T1_q_a[3]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[3]_PORT_B_address_reg = DFFE(T1_q_a[3]_PORT_B_address, T1_q_a[3]_clock_1, , , );
T1_q_a[3]_PORT_A_write_enable = GND;
T1_q_a[3]_PORT_A_write_enable_reg = DFFE(T1_q_a[3]_PORT_A_write_enable, T1_q_a[3]_clock_0, , , );
T1_q_a[3]_PORT_B_write_enable = U1L53;
T1_q_a[3]_PORT_B_write_enable_reg = DFFE(T1_q_a[3]_PORT_B_write_enable, T1_q_a[3]_clock_1, , , );
T1_q_a[3]_clock_0 = J1_clock0;
T1_q_a[3]_clock_1 = A1L5;
T1_q_a[3]_PORT_A_data_out = MEMORY(T1_q_a[3]_PORT_A_data_in_reg, T1_q_a[3]_PORT_B_data_in_reg, T1_q_a[3]_PORT_A_address_reg, T1_q_a[3]_PORT_B_address_reg, T1_q_a[3]_PORT_A_write_enable_reg, T1_q_a[3]_PORT_B_write_enable_reg, , , T1_q_a[3]_clock_0, T1_q_a[3]_clock_1, , , , );
T1_q_a[3]_PORT_A_data_out_reg = DFFE(T1_q_a[3]_PORT_A_data_out, T1_q_a[3]_clock_0, , , );
T1_q_a[3] = T1_q_a[3]_PORT_A_data_out_reg[0];

--T1_q_b[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[3]
T1_q_b[3]_PORT_A_data_in = VCC;
T1_q_b[3]_PORT_A_data_in_reg = DFFE(T1_q_b[3]_PORT_A_data_in, T1_q_b[3]_clock_0, , , );
T1_q_b[3]_PORT_B_data_in = U1_ram_rom_data_reg[3];
T1_q_b[3]_PORT_B_data_in_reg = DFFE(T1_q_b[3]_PORT_B_data_in, T1_q_b[3]_clock_1, , , );
T1_q_b[3]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[3]_PORT_A_address_reg = DFFE(T1_q_b[3]_PORT_A_address, T1_q_b[3]_clock_0, , , );
T1_q_b[3]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[3]_PORT_B_address_reg = DFFE(T1_q_b[3]_PORT_B_address, T1_q_b[3]_clock_1, , , );
T1_q_b[3]_PORT_A_write_enable = GND;
T1_q_b[3]_PORT_A_write_enable_reg = DFFE(T1_q_b[3]_PORT_A_write_enable, T1_q_b[3]_clock_0, , , );
T1_q_b[3]_PORT_B_write_enable = U1L53;
T1_q_b[3]_PORT_B_write_enable_reg = DFFE(T1_q_b[3]_PORT_B_write_enable, T1_q_b[3]_clock_1, , , );
T1_q_b[3]_clock_0 = J1_clock0;
T1_q_b[3]_clock_1 = A1L5;
T1_q_b[3]_PORT_B_data_out = MEMORY(T1_q_b[3]_PORT_A_data_in_reg, T1_q_b[3]_PORT_B_data_in_reg, T1_q_b[3]_PORT_A_address_reg, T1_q_b[3]_PORT_B_address_reg, T1_q_b[3]_PORT_A_write_enable_reg, T1_q_b[3]_PORT_B_write_enable_reg, , , T1_q_b[3]_clock_0, T1_q_b[3]_clock_1, , , , );
T1_q_b[3] = T1_q_b[3]_PORT_B_data_out[0];


--T1_q_a[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[2]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[2]_PORT_A_data_in = VCC;
T1_q_a[2]_PORT_A_data_in_reg = DFFE(T1_q_a[2]_PORT_A_data_in, T1_q_a[2]_clock_0, , , );
T1_q_a[2]_PORT_B_data_in = U1_ram_rom_data_reg[2];
T1_q_a[2]_PORT_B_data_in_reg = DFFE(T1_q_a[2]_PORT_B_data_in, T1_q_a[2]_clock_1, , , );
T1_q_a[2]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[2]_PORT_A_address_reg = DFFE(T1_q_a[2]_PORT_A_address, T1_q_a[2]_clock_0, , , );
T1_q_a[2]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[2]_PORT_B_address_reg = DFFE(T1_q_a[2]_PORT_B_address, T1_q_a[2]_clock_1, , , );
T1_q_a[2]_PORT_A_write_enable = GND;
T1_q_a[2]_PORT_A_write_enable_reg = DFFE(T1_q_a[2]_PORT_A_write_enable, T1_q_a[2]_clock_0, , , );
T1_q_a[2]_PORT_B_write_enable = U1L53;
T1_q_a[2]_PORT_B_write_enable_reg = DFFE(T1_q_a[2]_PORT_B_write_enable, T1_q_a[2]_clock_1, , , );
T1_q_a[2]_clock_0 = J1_clock0;
T1_q_a[2]_clock_1 = A1L5;
T1_q_a[2]_PORT_A_data_out = MEMORY(T1_q_a[2]_PORT_A_data_in_reg, T1_q_a[2]_PORT_B_data_in_reg, T1_q_a[2]_PORT_A_address_reg, T1_q_a[2]_PORT_B_address_reg, T1_q_a[2]_PORT_A_write_enable_reg, T1_q_a[2]_PORT_B_write_enable_reg, , , T1_q_a[2]_clock_0, T1_q_a[2]_clock_1, , , , );
T1_q_a[2]_PORT_A_data_out_reg = DFFE(T1_q_a[2]_PORT_A_data_out, T1_q_a[2]_clock_0, , , );
T1_q_a[2] = T1_q_a[2]_PORT_A_data_out_reg[0];

--T1_q_b[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[2]
T1_q_b[2]_PORT_A_data_in = VCC;
T1_q_b[2]_PORT_A_data_in_reg = DFFE(T1_q_b[2]_PORT_A_data_in, T1_q_b[2]_clock_0, , , );
T1_q_b[2]_PORT_B_data_in = U1_ram_rom_data_reg[2];
T1_q_b[2]_PORT_B_data_in_reg = DFFE(T1_q_b[2]_PORT_B_data_in, T1_q_b[2]_clock_1, , , );
T1_q_b[2]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[2]_PORT_A_address_reg = DFFE(T1_q_b[2]_PORT_A_address, T1_q_b[2]_clock_0, , , );
T1_q_b[2]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[2]_PORT_B_address_reg = DFFE(T1_q_b[2]_PORT_B_address, T1_q_b[2]_clock_1, , , );
T1_q_b[2]_PORT_A_write_enable = GND;
T1_q_b[2]_PORT_A_write_enable_reg = DFFE(T1_q_b[2]_PORT_A_write_enable, T1_q_b[2]_clock_0, , , );
T1_q_b[2]_PORT_B_write_enable = U1L53;
T1_q_b[2]_PORT_B_write_enable_reg = DFFE(T1_q_b[2]_PORT_B_write_enable, T1_q_b[2]_clock_1, , , );
T1_q_b[2]_clock_0 = J1_clock0;
T1_q_b[2]_clock_1 = A1L5;
T1_q_b[2]_PORT_B_data_out = MEMORY(T1_q_b[2]_PORT_A_data_in_reg, T1_q_b[2]_PORT_B_data_in_reg, T1_q_b[2]_PORT_A_address_reg, T1_q_b[2]_PORT_B_address_reg, T1_q_b[2]_PORT_A_write_enable_reg, T1_q_b[2]_PORT_B_write_enable_reg, , , T1_q_b[2]_clock_0, T1_q_b[2]_clock_1, , , , );
T1_q_b[2] = T1_q_b[2]_PORT_B_data_out[0];


--T1_q_a[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[1]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[1]_PORT_A_data_in = VCC;
T1_q_a[1]_PORT_A_data_in_reg = DFFE(T1_q_a[1]_PORT_A_data_in, T1_q_a[1]_clock_0, , , );
T1_q_a[1]_PORT_B_data_in = U1_ram_rom_data_reg[1];
T1_q_a[1]_PORT_B_data_in_reg = DFFE(T1_q_a[1]_PORT_B_data_in, T1_q_a[1]_clock_1, , , );
T1_q_a[1]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[1]_PORT_A_address_reg = DFFE(T1_q_a[1]_PORT_A_address, T1_q_a[1]_clock_0, , , );
T1_q_a[1]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[1]_PORT_B_address_reg = DFFE(T1_q_a[1]_PORT_B_address, T1_q_a[1]_clock_1, , , );
T1_q_a[1]_PORT_A_write_enable = GND;
T1_q_a[1]_PORT_A_write_enable_reg = DFFE(T1_q_a[1]_PORT_A_write_enable, T1_q_a[1]_clock_0, , , );
T1_q_a[1]_PORT_B_write_enable = U1L53;
T1_q_a[1]_PORT_B_write_enable_reg = DFFE(T1_q_a[1]_PORT_B_write_enable, T1_q_a[1]_clock_1, , , );
T1_q_a[1]_clock_0 = J1_clock0;
T1_q_a[1]_clock_1 = A1L5;
T1_q_a[1]_PORT_A_data_out = MEMORY(T1_q_a[1]_PORT_A_data_in_reg, T1_q_a[1]_PORT_B_data_in_reg, T1_q_a[1]_PORT_A_address_reg, T1_q_a[1]_PORT_B_address_reg, T1_q_a[1]_PORT_A_write_enable_reg, T1_q_a[1]_PORT_B_write_enable_reg, , , T1_q_a[1]_clock_0, T1_q_a[1]_clock_1, , , , );
T1_q_a[1]_PORT_A_data_out_reg = DFFE(T1_q_a[1]_PORT_A_data_out, T1_q_a[1]_clock_0, , , );
T1_q_a[1] = T1_q_a[1]_PORT_A_data_out_reg[0];

--T1_q_b[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[1]
T1_q_b[1]_PORT_A_data_in = VCC;
T1_q_b[1]_PORT_A_data_in_reg = DFFE(T1_q_b[1]_PORT_A_data_in, T1_q_b[1]_clock_0, , , );
T1_q_b[1]_PORT_B_data_in = U1_ram_rom_data_reg[1];
T1_q_b[1]_PORT_B_data_in_reg = DFFE(T1_q_b[1]_PORT_B_data_in, T1_q_b[1]_clock_1, , , );
T1_q_b[1]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[1]_PORT_A_address_reg = DFFE(T1_q_b[1]_PORT_A_address, T1_q_b[1]_clock_0, , , );
T1_q_b[1]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[1]_PORT_B_address_reg = DFFE(T1_q_b[1]_PORT_B_address, T1_q_b[1]_clock_1, , , );
T1_q_b[1]_PORT_A_write_enable = GND;
T1_q_b[1]_PORT_A_write_enable_reg = DFFE(T1_q_b[1]_PORT_A_write_enable, T1_q_b[1]_clock_0, , , );
T1_q_b[1]_PORT_B_write_enable = U1L53;
T1_q_b[1]_PORT_B_write_enable_reg = DFFE(T1_q_b[1]_PORT_B_write_enable, T1_q_b[1]_clock_1, , , );
T1_q_b[1]_clock_0 = J1_clock0;
T1_q_b[1]_clock_1 = A1L5;
T1_q_b[1]_PORT_B_data_out = MEMORY(T1_q_b[1]_PORT_A_data_in_reg, T1_q_b[1]_PORT_B_data_in_reg, T1_q_b[1]_PORT_A_address_reg, T1_q_b[1]_PORT_B_address_reg, T1_q_b[1]_PORT_A_write_enable_reg, T1_q_b[1]_PORT_B_write_enable_reg, , , T1_q_b[1]_clock_0, T1_q_b[1]_clock_1, , , , );
T1_q_b[1] = T1_q_b[1]_PORT_B_data_out[0];


--T1_q_a[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[0]
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 1, Port B Depth: 1024, Port B Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[0]_PORT_A_data_in = VCC;
T1_q_a[0]_PORT_A_data_in_reg = DFFE(T1_q_a[0]_PORT_A_data_in, T1_q_a[0]_clock_0, , , );
T1_q_a[0]_PORT_B_data_in = U1_ram_rom_data_reg[0];
T1_q_a[0]_PORT_B_data_in_reg = DFFE(T1_q_a[0]_PORT_B_data_in, T1_q_a[0]_clock_1, , , );
T1_q_a[0]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[0]_PORT_A_address_reg = DFFE(T1_q_a[0]_PORT_A_address, T1_q_a[0]_clock_0, , , );
T1_q_a[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[0]_PORT_B_address_reg = DFFE(T1_q_a[0]_PORT_B_address, T1_q_a[0]_clock_1, , , );
T1_q_a[0]_PORT_A_write_enable = GND;
T1_q_a[0]_PORT_A_write_enable_reg = DFFE(T1_q_a[0]_PORT_A_write_enable, T1_q_a[0]_clock_0, , , );
T1_q_a[0]_PORT_B_write_enable = U1L53;
T1_q_a[0]_PORT_B_write_enable_reg = DFFE(T1_q_a[0]_PORT_B_write_enable, T1_q_a[0]_clock_1, , , );
T1_q_a[0]_clock_0 = J1_clock0;
T1_q_a[0]_clock_1 = A1L5;
T1_q_a[0]_PORT_A_data_out = MEMORY(T1_q_a[0]_PORT_A_data_in_reg, T1_q_a[0]_PORT_B_data_in_reg, T1_q_a[0]_PORT_A_address_reg, T1_q_a[0]_PORT_B_address_reg, T1_q_a[0]_PORT_A_write_enable_reg, T1_q_a[0]_PORT_B_write_enable_reg, , , T1_q_a[0]_clock_0, T1_q_a[0]_clock_1, , , , );
T1_q_a[0]_PORT_A_data_out_reg = DFFE(T1_q_a[0]_PORT_A_data_out, T1_q_a[0]_clock_0, , , );
T1_q_a[0] = T1_q_a[0]_PORT_A_data_out_reg[0];

--T1_q_b[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[0]
T1_q_b[0]_PORT_A_data_in = VCC;
T1_q_b[0]_PORT_A_data_in_reg = DFFE(T1_q_b[0]_PORT_A_data_in, T1_q_b[0]_clock_0, , , );
T1_q_b[0]_PORT_B_data_in = U1_ram_rom_data_reg[0];
T1_q_b[0]_PORT_B_data_in_reg = DFFE(T1_q_b[0]_PORT_B_data_in, T1_q_b[0]_clock_1, , , );
T1_q_b[0]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[0]_PORT_A_address_reg = DFFE(T1_q_b[0]_PORT_A_address, T1_q_b[0]_clock_0, , , );
T1_q_b[0]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[0]_PORT_B_address_reg = DFFE(T1_q_b[0]_PORT_B_address, T1_q_b[0]_clock_1, , , );
T1_q_b[0]_PORT_A_write_enable = GND;
T1_q_b[0]_PORT_A_write_enable_reg = DFFE(T1_q_b[0]_PORT_A_write_enable, T1_q_b[0]_clock_0, , , );
T1_q_b[0]_PORT_B_write_enable = U1L53;
T1_q_b[0]_PORT_B_write_enable_reg = DFFE(T1_q_b[0]_PORT_B_write_enable, T1_q_b[0]_clock_1, , , );
T1_q_b[0]_clock_0 = J1_clock0;
T1_q_b[0]_clock_1 = A1L5;
T1_q_b[0]_PORT_B_data_out = MEMORY(T1_q_b[0]_PORT_A_data_in_reg, T1_q_b[0]_PORT_B_data_in_reg, T1_q_b[0]_PORT_A_address_reg, T1_q_b[0]_PORT_B_address_reg, T1_q_b[0]_PORT_A_write_enable_reg, T1_q_b[0]_PORT_B_write_enable_reg, , , T1_q_b[0]_clock_0, T1_q_b[0]_clock_1, , , , );
T1_q_b[0] = T1_q_b[0]_PORT_B_data_out[0];


--A1L6 is altera_internal_jtag~TDO
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L51Q);

--A1L7 is altera_internal_jtag~TMSUTAP
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L51Q);

--A1L5 is altera_internal_jtag~TCKUTAP
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L51Q);

--altera_internal_jtag is altera_internal_jtag
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L51Q);


--U1_ram_rom_incr_write_addr_reg is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_write_addr_reg
--operation mode is normal

U1_ram_rom_incr_write_addr_reg = AMPP_FUNCTION(A1L5, U1L83, VCC);


--K1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2]
--operation mode is normal

K1_Q[2] = AMPP_FUNCTION(A1L5, K2_Q[2], K6_Q[2], K3_Q[0], !B1L2, B1L91);


--U1L53 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~1
--operation mode is normal

U1L53 = AMPP_FUNCTION(U1_ram_rom_incr_write_addr_reg, K1_Q[2]);


--G1_dout[0] is reg10b:u5|dout[0]
--operation mode is arithmetic

G1_dout[0]_lut_out = D1_dout[22] $ pword[0];
G1_dout[0] = DFFEA(G1_dout[0]_lut_out, J1_clock0, Y1__locked, , , , );

--G1L3 is reg10b:u5|dout[0]~COUT
--operation mode is arithmetic

G1L3 = CARRY(D1_dout[22] & pword[0]);


--G1_dout[1] is reg10b:u5|dout[1]
--operation mode is arithmetic

G1_dout[1]_carry_eqn = G1L3;
G1_dout[1]_lut_out = D1_dout[23] $ pword[1] $ G1_dout[1]_carry_eqn;
G1_dout[1] = DFFEA(G1_dout[1]_lut_out, J1_clock0, Y1__locked, , , , );

--G1L5 is reg10b:u5|dout[1]~COUT
--operation mode is arithmetic

G1L5 = CARRY(D1_dout[23] & !pword[1] & !G1L3 # !D1_dout[23] & (!G1L3 # !pword[1]));


--G1_dout[2] is reg10b:u5|dout[2]
--operation mode is arithmetic