dds_vhdl.fit.summary

来自「基于fpga的正弦波发生器设计」· SUMMARY 代码 · 共 13 行

Fitter Status : Successful - Wed Nov 22 19:38:07 2006
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : dds_vhdl
Top-level Entity Name : dds_vhdl
Family : Cyclone
Device : EP1C3T144C8
Timing Models : Final
Total logic elements : 200 / 2,910 ( 7 % )
Total pins : 41 / 104 ( 39 % )
Total virtual pins : 0
Total memory bits : 10,240 / 59,904 ( 17 % )
Total PLLs : 1 / 1 ( 100 % )