dds_vhdl.hier_info

基于fpga的正弦波发生器设计

data_write[1] <= ram_rom_data_reg[1].DB_MAX_OUTPUT_PORT_TYPE
data_write[2] <= ram_rom_data_reg[2].DB_MAX_OUTPUT_PORT_TYPE
data_write[3] <= ram_rom_data_reg[3].DB_MAX_OUTPUT_PORT_TYPE
data_write[4] <= ram_rom_data_reg[4].DB_MAX_OUTPUT_PORT_TYPE
data_write[5] <= ram_rom_data_reg[5].DB_MAX_OUTPUT_PORT_TYPE
data_write[6] <= ram_rom_data_reg[6].DB_MAX_OUTPUT_PORT_TYPE
data_write[7] <= ram_rom_data_reg[7].DB_MAX_OUTPUT_PORT_TYPE
data_write[8] <= ram_rom_data_reg[8].DB_MAX_OUTPUT_PORT_TYPE
data_write[9] <= ram_rom_data_reg[9].DB_MAX_OUTPUT_PORT_TYPE
data_read[0] => ram_rom_data_reg~19.DATAB
data_read[1] => ram_rom_data_reg~18.DATAB
data_read[2] => ram_rom_data_reg~17.DATAB
data_read[3] => ram_rom_data_reg~16.DATAB
data_read[4] => ram_rom_data_reg~15.DATAB
data_read[5] => ram_rom_data_reg~14.DATAB
data_read[6] => ram_rom_data_reg~13.DATAB
data_read[7] => ram_rom_data_reg~12.DATAB
data_read[8] => ram_rom_data_reg~11.DATAB
data_read[9] => ram_rom_data_reg~10.DATAB
raw_tck => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.TCK
raw_tck => is_in_use_reg.CLK
raw_tck => bypass_reg_out.CLK
raw_tck => ir_loaded_address_reg[0].CLK
raw_tck => ir_loaded_address_reg[1].CLK
raw_tck => ir_loaded_address_reg[2].CLK
raw_tck => ir_loaded_address_reg[3].CLK
raw_tck => ram_rom_data_shift_cntr_reg[0].CLK
raw_tck => ram_rom_data_shift_cntr_reg[1].CLK
raw_tck => ram_rom_data_shift_cntr_reg[2].CLK
raw_tck => ram_rom_data_shift_cntr_reg[3].CLK
raw_tck => ram_rom_data_reg[0].CLK
raw_tck => ram_rom_data_reg[1].CLK
raw_tck => ram_rom_data_reg[2].CLK
raw_tck => ram_rom_data_reg[3].CLK
raw_tck => ram_rom_data_reg[4].CLK
raw_tck => ram_rom_data_reg[5].CLK
raw_tck => ram_rom_data_reg[6].CLK
raw_tck => ram_rom_data_reg[7].CLK
raw_tck => ram_rom_data_reg[8].CLK
raw_tck => ram_rom_data_reg[9].CLK
raw_tck => ram_rom_addr_reg[0].CLK
raw_tck => ram_rom_addr_reg[1].CLK
raw_tck => ram_rom_addr_reg[2].CLK
raw_tck => ram_rom_addr_reg[3].CLK
raw_tck => ram_rom_addr_reg[4].CLK
raw_tck => ram_rom_addr_reg[5].CLK
raw_tck => ram_rom_addr_reg[6].CLK
raw_tck => ram_rom_addr_reg[7].CLK
raw_tck => ram_rom_addr_reg[8].CLK
raw_tck => ram_rom_addr_reg[9].CLK
raw_tck => tck_usr.DATAIN
tdi => ram_rom_addr_reg~10.DATAB
tdi => ram_rom_data_reg~0.DATAB
tdi => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.TDI
tdi => bypass_reg_out.DATAIN
usr1 => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.USR1
usr1 => dr_scan.IN1
usr1 => no_name_gen~0.IN1
jtag_state_cdr => no_name_gen~1.IN1
jtag_state_sdr => sdr.IN1
jtag_state_sdr => no_name_gen~1.IN0
jtag_state_sdr => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.SHIFT
jtag_state_e1dr => ram_rom_update_write_ena.IN0
jtag_state_udr => udr.IN1
jtag_state_udr => sld_rom_sr:ram_rom_logic_gen:no_name_gen:info_rom_sr.UPDATE
jtag_state_uir => ~NO_FANOUT~
clrn => bypass_reg_out.ACLR
clrn => is_in_use_reg.ACLR
ena => dr_scan.IN0
ena => no_name_gen~0.IN0
ena => bypass_reg_out.ENA
ir_in[0] => process4~0.IN0
ir_in[0] => tdo~1.OUTPUTSELECT
ir_in[0] => is_in_use_reg~1.OUTPUTSELECT
ir_in[0] => ram_rom_addr_reg[0].ACLR
ir_in[0] => ram_rom_addr_reg[1].ACLR
ir_in[0] => ram_rom_addr_reg[2].ACLR
ir_in[0] => ram_rom_addr_reg[3].ACLR
ir_in[0] => ram_rom_addr_reg[4].ACLR
ir_in[0] => ram_rom_addr_reg[5].ACLR
ir_in[0] => ram_rom_addr_reg[6].ACLR
ir_in[0] => ram_rom_addr_reg[7].ACLR
ir_in[0] => ram_rom_addr_reg[8].ACLR
ir_in[0] => ram_rom_addr_reg[9].ACLR
ir_in[1] => process1~0.IN0
ir_in[1] => process1~2.IN0
ir_in[1] => ram_rom_incr_addr~0.IN0
ir_in[2] => process1~2.IN1
ir_in[2] => ram_rom_incr_addr~1.IN0
ir_in[2] => enable_write~0.IN1
ir_in[3] => process0~0.IN0
ir_in[3] => process1~1.IN0
ir_in[3] => process4~1.IN1
ir_in[3] => ram_rom_data_shift_cntr_reg[0].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[1].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[2].ACLR
ir_in[3] => ram_rom_data_shift_cntr_reg[3].ACLR
ir_in[4] => process4~0.IN1
ir_in[4] => is_in_use_reg~0.OUTPUTSELECT
ir_out[0] <= is_in_use_reg.DB_MAX_OUTPUT_PORT_TYPE
ir_out[1] <= ir_loaded_address_reg[0].DB_MAX_OUTPUT_PORT_TYPE
ir_out[2] <= ir_loaded_address_reg[1].DB_MAX_OUTPUT_PORT_TYPE
ir_out[3] <= ir_loaded_address_reg[2].DB_MAX_OUTPUT_PORT_TYPE
ir_out[4] <= ir_loaded_address_reg[3].DB_MAX_OUTPUT_PORT_TYPE
irq <= <GND>
tdo <= tdo~1.DB_MAX_OUTPUT_PORT_TYPE


|dds_vhdl|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr
ROM_DATA[0] => Mux3.IN66
ROM_DATA[1] => Mux2.IN66
ROM_DATA[2] => Mux1.IN66
ROM_DATA[3] => Mux0.IN66
ROM_DATA[4] => Mux3.IN62
ROM_DATA[5] => Mux2.IN62
ROM_DATA[6] => Mux1.IN62
ROM_DATA[7] => Mux0.IN62
ROM_DATA[8] => Mux3.IN58
ROM_DATA[9] => Mux2.IN58
ROM_DATA[10] => Mux1.IN58
ROM_DATA[11] => Mux0.IN58
ROM_DATA[12] => Mux3.IN54
ROM_DATA[13] => Mux2.IN54
ROM_DATA[14] => Mux1.IN54
ROM_DATA[15] => Mux0.IN54
ROM_DATA[16] => Mux3.IN50
ROM_DATA[17] => Mux2.IN50
ROM_DATA[18] => Mux1.IN50
ROM_DATA[19] => Mux0.IN50
ROM_DATA[20] => Mux3.IN46
ROM_DATA[21] => Mux2.IN46
ROM_DATA[22] => Mux1.IN46
ROM_DATA[23] => Mux0.IN46
ROM_DATA[24] => Mux3.IN42
ROM_DATA[25] => Mux2.IN42
ROM_DATA[26] => Mux1.IN42
ROM_DATA[27] => Mux0.IN42
ROM_DATA[28] => Mux3.IN38
ROM_DATA[29] => Mux2.IN38
ROM_DATA[30] => Mux1.IN38
ROM_DATA[31] => Mux0.IN38
ROM_DATA[32] => Mux3.IN34
ROM_DATA[33] => Mux2.IN34
ROM_DATA[34] => Mux1.IN34
ROM_DATA[35] => Mux0.IN34
ROM_DATA[36] => Mux3.IN30
ROM_DATA[37] => Mux2.IN30
ROM_DATA[38] => Mux1.IN30
ROM_DATA[39] => Mux0.IN30
ROM_DATA[40] => Mux3.IN26
ROM_DATA[41] => Mux2.IN26
ROM_DATA[42] => Mux1.IN26
ROM_DATA[43] => Mux0.IN26
ROM_DATA[44] => Mux3.IN22
ROM_DATA[45] => Mux2.IN22
ROM_DATA[46] => Mux1.IN22
ROM_DATA[47] => Mux0.IN22
TCK => WORD_SR[0].CLK
TCK => WORD_SR[1].CLK
TCK => WORD_SR[2].CLK
TCK => WORD_SR[3].CLK
TCK => word_counter[0].CLK
TCK => word_counter[1].CLK
TCK => word_counter[2].CLK
TCK => word_counter[3].CLK
SHIFT => word_counter~4.OUTPUTSELECT
SHIFT => word_counter~5.OUTPUTSELECT
SHIFT => word_counter~6.OUTPUTSELECT
SHIFT => word_counter~7.OUTPUTSELECT
SHIFT => WORD_SR~0.OUTPUTSELECT
SHIFT => WORD_SR~1.OUTPUTSELECT
SHIFT => WORD_SR~2.OUTPUTSELECT
SHIFT => WORD_SR~3.OUTPUTSELECT
UPDATE => clear_signal.IN0
USR1 => clear_signal.IN1
ENA => word_counter~8.OUTPUTSELECT
ENA => word_counter~9.OUTPUTSELECT
ENA => word_counter~10.OUTPUTSELECT
ENA => word_counter~11.OUTPUTSELECT
ENA => WORD_SR~4.OUTPUTSELECT
ENA => WORD_SR~5.OUTPUTSELECT
ENA => WORD_SR~6.OUTPUTSELECT
ENA => WORD_SR~7.OUTPUTSELECT
TDI => WORD_SR~0.DATAA
TDO <= WORD_SR[0].DB_MAX_OUTPUT_PORT_TYPE


|dds_vhdl|adder10b:u4
a[0] => Add0.IN10
a[1] => Add0.IN9
a[2] => Add0.IN8
a[3] => Add0.IN7
a[4] => Add0.IN6
a[5] => Add0.IN5
a[6] => Add0.IN4
a[7] => Add0.IN3
a[8] => Add0.IN2
a[9] => Add0.IN1
b[0] => Add0.IN20
b[1] => Add0.IN19
b[2] => Add0.IN18
b[3] => Add0.IN17
b[4] => Add0.IN16
b[5] => Add0.IN15
b[6] => Add0.IN14
b[7] => Add0.IN13
b[8] => Add0.IN12
b[9] => Add0.IN11
s[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
s[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|dds_vhdl|reg10b:u5
load => dout[0]~reg0.CLK
load => dout[1]~reg0.CLK
load => dout[2]~reg0.CLK
load => dout[3]~reg0.CLK
load => dout[4]~reg0.CLK
load => dout[5]~reg0.CLK
load => dout[6]~reg0.CLK
load => dout[7]~reg0.CLK
load => dout[8]~reg0.CLK
load => dout[9]~reg0.CLK
rst10 => dout[0]~reg0.ACLR
rst10 => dout[1]~reg0.ACLR
rst10 => dout[2]~reg0.ACLR
rst10 => dout[3]~reg0.ACLR
rst10 => dout[4]~reg0.ACLR
rst10 => dout[5]~reg0.ACLR
rst10 => dout[6]~reg0.ACLR
rst10 => dout[7]~reg0.ACLR
rst10 => dout[8]~reg0.ACLR
rst10 => dout[9]~reg0.ACLR
din[0] => dout[0]~reg0.DATAIN
din[1] => dout[1]~reg0.DATAIN
din[2] => dout[2]~reg0.DATAIN
din[3] => dout[3]~reg0.DATAIN
din[4] => dout[4]~reg0.DATAIN
din[5] => dout[5]~reg0.DATAIN
din[6] => dout[6]~reg0.DATAIN
din[7] => dout[7]~reg0.DATAIN
din[8] => dout[8]~reg0.DATAIN
din[9] => dout[9]~reg0.DATAIN
dout[0] <= dout[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[1] <= dout[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[2] <= dout[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[3] <= dout[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[4] <= dout[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[5] <= dout[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[6] <= dout[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[7] <= dout[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[8] <= dout[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
dout[9] <= dout[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|dds_vhdl|pll1:u6
inclk0 => altpll:altpll_component.inclk[0]
c0 <= altpll:altpll_component.clk[0]
locked <= altpll:altpll_component.locked


|dds_vhdl|pll1:u6|altpll:altpll_component
inclk[0] => pll.CLK
inclk[1] => pll.CLK1
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
clk[0] <= pll.CLK
clk[1] <= <UNC>
clk[2] <= <UNC>
clk[3] <= <UNC>
clk[4] <= <UNC>
clk[5] <= <UNC>
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= pll.LOCKED
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= sclkout1~0.DB_MAX_OUTPUT_PORT_TYPE


|dds_vhdl|and2ab:u7
a => clock0~0.IN0
b => clock0~0.IN1
clock0 <= clock0~0.DB_MAX_OUTPUT_PORT_TYPE