dds_vhdl.fit.qmsg

基于fpga的正弦波发生器设计

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_RAM_METASTABILITY_INFO" "" "Info: Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." {  } {  } 0 0 "Design uses memory blocks. Violating setup or hold times of memory block address registers could cause memory contents to be corrupted. Make sure that all memory block address registers meet the setup and hold time requirements." 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Node sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sld_hub:sld_hub_inst\|jtag_debug_mode " "Info: Port clear -- assigned as a global for destination node sld_hub:sld_hub_inst\|jtag_debug_mode -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|jtag_debug_mode" } } } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 392 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|jtag_debug_mode } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]" } } } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[0] } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE_TOP_MSG" "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " "Info: Node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 uses non-global routing resources to route signals to global destination nodes" { { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[0\]" } } } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 576 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[0] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[3\]" } } } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 576 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[3] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[1\]" } } } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 576 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[1] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0} { "Info" "IFSAC_FSAC_GLOBAL_CLK_USES_LAB_LINE" "clear sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] " "Info: Port clear -- assigned as a global for destination node sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\] -- routed using non-global resources" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|ir_loaded_address_reg\[2\]" } } } } { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 576 -1 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ir_loaded_address_reg[2] } "NODE_NAME" } }  } 0 0 "Port %1!s! -- assigned as a global for destination node %2!s! -- routed using non-global resources" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } }  } 0 0 "Node %1!s! uses non-global routing resources to route signals to global destination nodes" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Nov 22 19:38:07 2006 " "Info: Processing ended: Wed Nov 22 19:38:07 2006" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:12 " "Info: Elapsed time: 00:00:12" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/lgQ/EDA/peda/sin/dds_vhdl.fit.smsg " "Info: Generated suppressed messages file E:/lgQ/EDA/peda/sin/dds_vhdl.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}