dds_vhdl.fit.qmsg

基于fpga的正弦波发生器设计

{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_GLOBAL_LINES_NEEDED_FOR_TORNADO_DQS" "0 " "Info: DQS I/O pins require 0 global routing resources" {  } {  } 0 0 "DQS I/O pins require %1!d! global routing resources" 0 0}
{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK_USER" "pll1:u6\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"pll1:u6\|altpll:altpll_component\|_clk0\" to use global clock (user assigned)" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "pll1:u6\|altpll:altpll_component\|_clk0" } { 0 "pll1:u6\|altpll:altpll_component\|_clk0" } } } } { "dds_vhdl.vhd" "" { Text "E:/lgQ/EDA/peda/sin/dds_vhdl.vhd" 68 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll1:u6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll1:u6|altpll:altpll_component|_clk0 } "NODE_NAME" } }  } 0 0 "Promoted signal \"%1!s!\" to use global clock (user assigned)" 0 0}  } {  } 0 0 "Promoted PLL clock signals" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "altera_internal_jtag~TCKUTAP Global clock " "Info: Automatically promoted signal \"altera_internal_jtag~TCKUTAP\" to use Global clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "altera_internal_jtag~TDO" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TDO } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "and2ab:u7\|clock0 Global clock " "Info: Automatically promoted some destinations of signal \"and2ab:u7\|clock0\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "as " "Info: Destination \"as\" may be non-global or may not use global clock" {  } { { "dds_vhdl.vhd" "" { Text "E:/lgQ/EDA/peda/sin/dds_vhdl.vhd" 6 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "and2ab.vhd" "" { Text "E:/lgQ/EDA/peda/sin/and2ab.vhd" 5 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sld_hub:sld_hub_inst\|CLR_SIGNAL Global clock " "Info: Automatically promoted signal \"sld_hub:sld_hub_inst\|CLR_SIGNAL\" to use Global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 316 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[0\]\" may be non-global or may not use global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\] " "Info: Destination \"sld_hub:sld_hub_inst\|sld_jtag_state_machine:jtag_state_machine\|state\[1\]\" may be non-global or may not use global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 1150 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[0\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~541 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~541\" may be non-global or may not use global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sld_hub:sld_hub_inst\|hub_tdo~542 " "Info: Destination \"sld_hub:sld_hub_inst\|hub_tdo~542\" may be non-global or may not use global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg " "Info: Destination \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|is_in_use_reg\" may be non-global or may not use global clock" {  } { { "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_mod_ram_rom.vhd" 708 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 " "Info: Destination \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0 Global clock " "Info: Automatically promoted signal \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0\" to use Global clock" {  } { { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~0" } } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|process4~0 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\] Global clock " "Info: Automatically promoted some destinations of signal \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[3\]\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1 " "Info: Destination \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process1~1\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~11 " "Info: Destination \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process0~11\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~13 " "Info: Destination \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|sld_mod_ram_rom:mgl_prim2\|process4~13\" may be non-global or may not use global clock" {  } {  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}