dds_vhdl.tan.qmsg

基于fpga的正弦波发生器设计

{ "Info" "ITDB_FULL_TCO_RESULT" "clk fout\[4\] sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|q_a\[4\] 10.334 ns memory " "Info: tco from clock \"clk\" to destination pin \"fout\[4\]\" through memory \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|q_a\[4\]\" is 10.334 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "clk pll1:u6\|altpll:altpll_component\|_clk0 -1.833 ns + " "Info: + Offset between input clock \"clk\" and output clock \"pll1:u6\|altpll:altpll_component\|_clk0\" is -1.833 ns" {  } { { "dds_vhdl.vhd" "" { Text "E:/lgQ/EDA/peda/sin/dds_vhdl.vhd" 5 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll1:u6\|altpll:altpll_component\|_clk0 source 6.385 ns + Longest memory " "Info: + Longest clock path from clock \"pll1:u6\|altpll:altpll_component\|_clk0\" to source memory is 6.385 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll1:u6\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll1:u6\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll1:u6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.104 ns) + CELL(0.114 ns) 2.218 ns and2ab:u7\|clock0 2 COMB LC_X8_Y6_N9 100 " "Info: 2: + IC(2.104 ns) + CELL(0.114 ns) = 2.218 ns; Loc. = LC_X8_Y6_N9; Fanout = 100; COMB Node = 'and2ab:u7\|clock0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 } "NODE_NAME" } } { "and2ab.vhd" "" { Text "E:/lgQ/EDA/peda/sin/and2ab.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.459 ns) + CELL(0.708 ns) 6.385 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto