📄 dds_vhdl.tan.qmsg
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{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "altera_internal_jtag~TCKUTAP register sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] register sld_hub:sld_hub_inst\|hub_tdo 93.18 MHz 10.732 ns Internal " "Info: Clock \"altera_internal_jtag~TCKUTAP\" has Internal fmax of 93.18 MHz between source register \"sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]\" and destination register \"sld_hub:sld_hub_inst\|hub_tdo\" (period= 10.732 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.105 ns + Longest register register " "Info: + Longest register to register delay is 5.105 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] 1 REG LC_X23_Y8_N3 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X23_Y8_N3; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.655 ns) + CELL(0.292 ns) 1.947 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]~209 2 COMB LC_X22_Y7_N0 3 " "Info: 2: + IC(1.655 ns) + CELL(0.292 ns) = 1.947 ns; Loc. = LC_X22_Y7_N0; Fanout = 3; COMB Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]~209'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.947 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.454 ns) + CELL(0.114 ns) 2.515 ns sld_hub:sld_hub_inst\|hub_tdo~541 3 COMB LC_X22_Y7_N3 1 " "Info: 3: + IC(0.454 ns) + CELL(0.114 ns) = 2.515 ns; Loc. = LC_X22_Y7_N3; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~541'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.568 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 sld_hub:sld_hub_inst|hub_tdo~541 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.440 ns) + CELL(0.114 ns) 3.069 ns sld_hub:sld_hub_inst\|hub_tdo~542 4 COMB LC_X22_Y7_N1 1 " "Info: 4: + IC(0.440 ns) + CELL(0.114 ns) = 3.069 ns; Loc. = LC_X22_Y7_N1; Fanout = 1; COMB Node = 'sld_hub:sld_hub_inst\|hub_tdo~542'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.554 ns" { sld_hub:sld_hub_inst|hub_tdo~541 sld_hub:sld_hub_inst|hub_tdo~542 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.558 ns) + CELL(0.478 ns) 5.105 ns sld_hub:sld_hub_inst\|hub_tdo 5 REG LC_X21_Y8_N5 1 " "Info: 5: + IC(1.558 ns) + CELL(0.478 ns) = 5.105 ns; Loc. = LC_X21_Y8_N5; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.036 ns" { sld_hub:sld_hub_inst|hub_tdo~542 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.998 ns ( 19.55 % ) " "Info: Total cell delay = 0.998 ns ( 19.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.107 ns ( 80.45 % ) " "Info: Total interconnect delay = 4.107 ns ( 80.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.105 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 sld_hub:sld_hub_inst|hub_tdo~541 sld_hub:sld_hub_inst|hub_tdo~542 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.105 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 sld_hub:sld_hub_inst|hub_tdo~541 sld_hub:sld_hub_inst|hub_tdo~542 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.655ns 0.454ns 0.440ns 1.558ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.478ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP destination 5.272 ns + Shortest register " "Info: + Shortest clock path from clock \"altera_internal_jtag~TCKUTAP\" to destination register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 161 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 161; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|hub_tdo 2 REG LC_X21_Y8_N5 1 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X21_Y8_N5; Fanout = 1; REG Node = 'sld_hub:sld_hub_inst\|hub_tdo'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "altera_internal_jtag~TCKUTAP source 5.272 ns - Longest register " "Info: - Longest clock path from clock \"altera_internal_jtag~TCKUTAP\" to source register is 5.272 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns altera_internal_jtag~TCKUTAP 1 CLK JTAG_X1_Y6_N1 161 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = JTAG_X1_Y6_N1; Fanout = 161; CLK Node = 'altera_internal_jtag~TCKUTAP'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { altera_internal_jtag~TCKUTAP } "NODE_NAME" } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(4.561 ns) + CELL(0.711 ns) 5.272 ns sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\] 2 REG LC_X23_Y8_N3 4 " "Info: 2: + IC(4.561 ns) + CELL(0.711 ns) = 5.272 ns; Loc. = LC_X23_Y8_N3; Fanout = 4; REG Node = 'sld_hub:sld_hub_inst\|sld_dffex:\\GEN_IRF:1:IRF\|Q\[1\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.711 ns ( 13.49 % ) " "Info: Total cell delay = 0.711 ns ( 13.49 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.561 ns ( 86.51 % ) " "Info: Total interconnect delay = 4.561 ns ( 86.51 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns + " "Info: + Micro clock to output delay of source is 0.224 ns" { } { { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_dffex.vhd" 19 -1 0 } } { "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" "" { Text "c:/altera/quartus60/libraries/megafunctions/sld_hub.vhd" 135 -1 0 } } } 0 0 "Delay path is controlled by inverted clocks -- if clock duty cycle is 50%, fmax is divided by two" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.105 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 sld_hub:sld_hub_inst|hub_tdo~541 sld_hub:sld_hub_inst|hub_tdo~542 sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.105 ns" { sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]~209 sld_hub:sld_hub_inst|hub_tdo~541 sld_hub:sld_hub_inst|hub_tdo~542 sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 1.655ns 0.454ns 0.440ns 1.558ns } { 0.000ns 0.292ns 0.114ns 0.114ns 0.478ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|hub_tdo } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.272 ns" { altera_internal_jtag~TCKUTAP sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1] } { 0.000ns 4.561ns } { 0.000ns 0.711ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "pll1:u6\|altpll:altpll_component\|_clk0 register reg32b:u2\|dout\[28\] register reg32b:u2\|dout\[28\] 1.314 ns " "Info: Minimum slack time is 1.314 ns for clock \"pll1:u6\|altpll:altpll_component\|_clk0\" between source register \"reg32b:u2\|dout\[28\]\" and destination register \"reg32b:u2\|dout\[28\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.105 ns + Shortest register register " "Info: + Shortest register to register delay is 1.105 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns reg32b:u2\|dout\[28\] 1 REG LC_X8_Y6_N4 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'reg32b:u2\|dout\[28\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { reg32b:u2|dout[28] } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.498 ns) + CELL(0.607 ns) 1.105 ns reg32b:u2\|dout\[28\] 2 REG LC_X8_Y6_N4 5 " "Info: 2: + IC(0.498 ns) + CELL(0.607 ns) = 1.105 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'reg32b:u2\|dout\[28\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.105 ns" { reg32b:u2|dout[28] reg32b:u2|dout[28] } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.607 ns ( 54.93 % ) " "Info: Total cell delay = 0.607 ns ( 54.93 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.498 ns ( 45.07 % ) " "Info: Total interconnect delay = 0.498 ns ( 45.07 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.105 ns" { reg32b:u2|dout[28] reg32b:u2|dout[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.105 ns" { reg32b:u2|dout[28] reg32b:u2|dout[28] } { 0.000ns 0.498ns } { 0.000ns 0.607ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.209 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.209 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.833 ns " "Info: + Latch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll1:u6\|altpll:altpll_component\|_clk0 15.000 ns -1.833 ns 50 " "Info: Clock period of Destination clock \"pll1:u6\|altpll:altpll_component\|_clk0\" is 15.000 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll1:u6\|altpll:altpll_component\|_clk0 15.000 ns -1.833 ns 50 " "Info: Clock period of Source clock \"pll1:u6\|altpll:altpll_component\|_clk0\" is 15.000 ns with offset of -1.833 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll1:u6\|altpll:altpll_component\|_clk0 destination 6.344 ns + Longest register " "Info: + Longest clock path from clock \"pll1:u6\|altpll:altpll_component\|_clk0\" to destination register is 6.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll1:u6\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll1:u6\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll1:u6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.104 ns) + CELL(0.114 ns) 2.218 ns and2ab:u7\|clock0 2 COMB LC_X8_Y6_N9 100 " "Info: 2: + IC(2.104 ns) + CELL(0.114 ns) = 2.218 ns; Loc. = LC_X8_Y6_N9; Fanout = 100; COMB Node = 'and2ab:u7\|clock0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 } "NODE_NAME" } } { "and2ab.vhd" "" { Text "E:/lgQ/EDA/peda/sin/and2ab.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.415 ns) + CELL(0.711 ns) 6.344 ns reg32b:u2\|dout\[28\] 3 REG LC_X8_Y6_N4 5 " "Info: 3: + IC(3.415 ns) + CELL(0.711 ns) = 6.344 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'reg32b:u2\|dout\[28\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.126 ns" { and2ab:u7|clock0 reg32b:u2|dout[28] } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.825 ns ( 13.00 % ) " "Info: Total cell delay = 0.825 ns ( 13.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.519 ns ( 87.00 % ) " "Info: Total interconnect delay = 5.519 ns ( 87.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } { 0.000ns 2.104ns 3.415ns } { 0.000ns 0.114ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll1:u6\|altpll:altpll_component\|_clk0 source 6.344 ns - Shortest register " "Info: - Shortest clock path from clock \"pll1:u6\|altpll:altpll_component\|_clk0\" to source register is 6.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll1:u6\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll1:u6\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll1:u6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.104 ns) + CELL(0.114 ns) 2.218 ns and2ab:u7\|clock0 2 COMB LC_X8_Y6_N9 100 " "Info: 2: + IC(2.104 ns) + CELL(0.114 ns) = 2.218 ns; Loc. = LC_X8_Y6_N9; Fanout = 100; COMB Node = 'and2ab:u7\|clock0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 } "NODE_NAME" } } { "and2ab.vhd" "" { Text "E:/lgQ/EDA/peda/sin/and2ab.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.415 ns) + CELL(0.711 ns) 6.344 ns reg32b:u2\|dout\[28\] 3 REG LC_X8_Y6_N4 5 " "Info: 3: + IC(3.415 ns) + CELL(0.711 ns) = 6.344 ns; Loc. = LC_X8_Y6_N4; Fanout = 5; REG Node = 'reg32b:u2\|dout\[28\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.126 ns" { and2ab:u7|clock0 reg32b:u2|dout[28] } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.825 ns ( 13.00 % ) " "Info: Total cell delay = 0.825 ns ( 13.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.519 ns ( 87.00 % ) " "Info: Total interconnect delay = 5.519 ns ( 87.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } { 0.000ns 2.104ns 3.415ns } { 0.000ns 0.114ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } { 0.000ns 2.104ns 3.415ns } { 0.000ns 0.114ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } { 0.000ns 2.104ns 3.415ns } { 0.000ns 0.114ns 0.711ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.224 ns - " "Info: - Micro clock to output delay of source is 0.224 ns" { } { { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.015 ns + " "Info: + Micro hold delay of destination is 0.015 ns" { } { { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } { 0.000ns 2.104ns 3.415ns } { 0.000ns 0.114ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } { 0.000ns 2.104ns 3.415ns } { 0.000ns 0.114ns 0.711ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.105 ns" { reg32b:u2|dout[28] reg32b:u2|dout[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.105 ns" { reg32b:u2|dout[28] reg32b:u2|dout[28] } { 0.000ns 0.498ns } { 0.000ns 0.607ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } { 0.000ns 2.104ns 3.415ns } { 0.000ns 0.114ns 0.711ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[28] } { 0.000ns 2.104ns 3.415ns } { 0.000ns 0.114ns 0.711ns } } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "reg32b:u2\|dout\[29\] fword\[9\] clk 5.301 ns register " "Info: tsu for register \"reg32b:u2\|dout\[29\]\" (data pin = \"fword\[9\]\", clock pin = \"clk\") is 5.301 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.775 ns + Longest pin register " "Info: + Longest pin to register delay is 9.775 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.469 ns) 1.469 ns fword\[9\] 1 PIN PIN_85 3 " "Info: 1: + IC(0.000 ns) + CELL(1.469 ns) = 1.469 ns; Loc. = PIN_85; Fanout = 3; PIN Node = 'fword\[9\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { fword[9] } "NODE_NAME" } } { "dds_vhdl.vhd" "" { Text "E:/lgQ/EDA/peda/sin/dds_vhdl.vhd" 7 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(6.366 ns) + CELL(0.423 ns) 8.258 ns reg32b:u2\|dout\[15\]~126 2 COMB LC_X8_Y7_N1 2 " "Info: 2: + IC(6.366 ns) + CELL(0.423 ns) = 8.258 ns; Loc. = LC_X8_Y7_N1; Fanout = 2; COMB Node = 'reg32b:u2\|dout\[15\]~126'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.789 ns" { fword[9] reg32b:u2|dout[15]~126 } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 8.336 ns reg32b:u2\|dout\[16\]~125 3 COMB LC_X8_Y7_N2 2 " "Info: 3: + IC(0.000 ns) + CELL(0.078 ns) = 8.336 ns; Loc. = LC_X8_Y7_N2; Fanout = 2; COMB Node = 'reg32b:u2\|dout\[16\]~125'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { reg32b:u2|dout[15]~126 reg32b:u2|dout[16]~125 } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.078 ns) 8.414 ns reg32b:u2\|dout\[17\]~124 4 COMB LC_X8_Y7_N3 2 " "Info: 4: + IC(0.000 ns) + CELL(0.078 ns) = 8.414 ns; Loc. = LC_X8_Y7_N3; Fanout = 2; COMB Node = 'reg32b:u2\|dout\[17\]~124'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.078 ns" { reg32b:u2|dout[16]~125 reg32b:u2|dout[17]~124 } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.178 ns) 8.592 ns reg32b:u2\|dout\[18\]~123 5 COMB LC_X8_Y7_N4 6 " "Info: 5: + IC(0.000 ns) + CELL(0.178 ns) = 8.592 ns; Loc. = LC_X8_Y7_N4; Fanout = 6; COMB Node = 'reg32b:u2\|dout\[18\]~123'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.178 ns" { reg32b:u2|dout[17]~124 reg32b:u2|dout[18]~123 } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.208 ns) 8.800 ns reg32b:u2\|dout\[23\]~111 6 COMB LC_X8_Y7_N9 6 " "Info: 6: + IC(0.000 ns) + CELL(0.208 ns) = 8.800 ns; Loc. = LC_X8_Y7_N9; Fanout = 6; COMB Node = 'reg32b:u2\|dout\[23\]~111'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.208 ns" { reg32b:u2|dout[18]~123 reg32b:u2|dout[23]~111 } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.136 ns) 8.936 ns reg32b:u2\|dout\[28\]~116 7 COMB LC_X8_Y6_N4 3 " "Info: 7: + IC(0.000 ns) + CELL(0.136 ns) = 8.936 ns; Loc. = LC_X8_Y6_N4; Fanout = 3; COMB Node = 'reg32b:u2\|dout\[28\]~116'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.136 ns" { reg32b:u2|dout[23]~111 reg32b:u2|dout[28]~116 } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.839 ns) 9.775 ns reg32b:u2\|dout\[29\] 8 REG LC_X8_Y6_N5 6 " "Info: 8: + IC(0.000 ns) + CELL(0.839 ns) = 9.775 ns; Loc. = LC_X8_Y6_N5; Fanout = 6; REG Node = 'reg32b:u2\|dout\[29\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.839 ns" { reg32b:u2|dout[28]~116 reg32b:u2|dout[29] } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.409 ns ( 34.87 % ) " "Info: Total cell delay = 3.409 ns ( 34.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.366 ns ( 65.13 % ) " "Info: Total interconnect delay = 6.366 ns ( 65.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.775 ns" { fword[9] reg32b:u2|dout[15]~126 reg32b:u2|dout[16]~125 reg32b:u2|dout[17]~124 reg32b:u2|dout[18]~123 reg32b:u2|dout[23]~111 reg32b:u2|dout[28]~116 reg32b:u2|dout[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.775 ns" { fword[9] fword[9]~out0 reg32b:u2|dout[15]~126 reg32b:u2|dout[16]~125 reg32b:u2|dout[17]~124 reg32b:u2|dout[18]~123 reg32b:u2|dout[23]~111 reg32b:u2|dout[28]~116 reg32b:u2|dout[29] } { 0.000ns 0.000ns 6.366ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.423ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.037 ns + " "Info: + Micro setup delay of destination is 0.037 ns" { } { { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_PLL_OFFSET" "clk pll1:u6\|altpll:altpll_component\|_clk0 -1.833 ns - " "Info: - Offset between input clock \"clk\" and output clock \"pll1:u6\|altpll:altpll_component\|_clk0\" is -1.833 ns" { } { { "dds_vhdl.vhd" "" { Text "E:/lgQ/EDA/peda/sin/dds_vhdl.vhd" 5 -1 0 } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll1:u6\|altpll:altpll_component\|_clk0 destination 6.344 ns - Shortest register " "Info: - Shortest clock path from clock \"pll1:u6\|altpll:altpll_component\|_clk0\" to destination register is 6.344 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll1:u6\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll1:u6\|altpll:altpll_component\|_clk0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll1:u6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.104 ns) + CELL(0.114 ns) 2.218 ns and2ab:u7\|clock0 2 COMB LC_X8_Y6_N9 100 " "Info: 2: + IC(2.104 ns) + CELL(0.114 ns) = 2.218 ns; Loc. = LC_X8_Y6_N9; Fanout = 100; COMB Node = 'and2ab:u7\|clock0'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 } "NODE_NAME" } } { "and2ab.vhd" "" { Text "E:/lgQ/EDA/peda/sin/and2ab.vhd" 5 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.415 ns) + CELL(0.711 ns) 6.344 ns reg32b:u2\|dout\[29\] 3 REG LC_X8_Y6_N5 6 " "Info: 3: + IC(3.415 ns) + CELL(0.711 ns) = 6.344 ns; Loc. = LC_X8_Y6_N5; Fanout = 6; REG Node = 'reg32b:u2\|dout\[29\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.126 ns" { and2ab:u7|clock0 reg32b:u2|dout[29] } "NODE_NAME" } } { "reg32b.vhd" "" { Text "E:/lgQ/EDA/peda/sin/reg32b.vhd" 12 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.825 ns ( 13.00 % ) " "Info: Total cell delay = 0.825 ns ( 13.00 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.519 ns ( 87.00 % ) " "Info: Total interconnect delay = 5.519 ns ( 87.00 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[29] } { 0.000ns 2.104ns 3.415ns } { 0.000ns 0.114ns 0.711ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.775 ns" { fword[9] reg32b:u2|dout[15]~126 reg32b:u2|dout[16]~125 reg32b:u2|dout[17]~124 reg32b:u2|dout[18]~123 reg32b:u2|dout[23]~111 reg32b:u2|dout[28]~116 reg32b:u2|dout[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.775 ns" { fword[9] fword[9]~out0 reg32b:u2|dout[15]~126 reg32b:u2|dout[16]~125 reg32b:u2|dout[17]~124 reg32b:u2|dout[18]~123 reg32b:u2|dout[23]~111 reg32b:u2|dout[28]~116 reg32b:u2|dout[29] } { 0.000ns 0.000ns 6.366ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns } { 0.000ns 1.469ns 0.423ns 0.078ns 0.078ns 0.178ns 0.208ns 0.136ns 0.839ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[29] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.344 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 reg32b:u2|dout[29] } { 0.000ns 2.104ns 3.415ns } { 0.000ns 0.114ns 0.711ns } } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
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