dds_vhdl.tan.qmsg

基于fpga的正弦波发生器设计

{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" {  } {  } 0 0 "Found timing assignments -- calculating delays" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "pll1:u6\|altpll:altpll_component\|_clk0 memory sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_datain_reg1 memory sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_memory_reg1 9.924 ns " "Info: Slack time is 9.924 ns for clock \"pll1:u6\|altpll:altpll_component\|_clk0\" between source memory \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_datain_reg1\" and destination memory \"sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_memory_reg1\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "197.01 MHz 5.076 ns " "Info: Fmax is 197.01 MHz (period= 5.076 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "14.243 ns + Largest memory memory " "Info: + Largest memory to memory requirement is 14.243 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "15.000 ns + " "Info: + Setup relationship between source and destination is 15.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 13.167 ns " "Info: + Latch edge is 13.167 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination pll1:u6\|altpll:altpll_component\|_clk0 15.000 ns -1.833 ns  50 " "Info: Clock period of Destination clock \"pll1:u6\|altpll:altpll_component\|_clk0\" is 15.000 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.833 ns " "Info: - Launch edge is -1.833 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source pll1:u6\|altpll:altpll_component\|_clk0 15.000 ns -1.833 ns  50 " "Info: Clock period of Source clock \"pll1:u6\|altpll:altpll_component\|_clk0\" is 15.000 ns with  offset of -1.833 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.014 ns + Largest " "Info: + Largest clock skew is -0.014 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll1:u6\|altpll:altpll_component\|_clk0 destination 6.384 ns + Shortest memory " "Info: + Shortest clock path from clock \"pll1:u6\|altpll:altpll_component\|_clk0\" to destination memory is 6.384 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll1:u6\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll1:u6\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll1:u6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.104 ns) + CELL(0.114 ns) 2.218 ns and2ab:u7\|clock0 2 COMB LC_X8_Y6_N9 100 " "Info: 2: + IC(2.104 ns) + CELL(0.114 ns) = 2.218 ns; Loc. = LC_X8_Y6_N9; Fanout = 100; COMB Node = 'and2ab:u7\|clock0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 } "NODE_NAME" } } { "and2ab.vhd" "" { Text "E:/lgQ/EDA/peda/sin/and2ab.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.458 ns) + CELL(0.708 ns) 6.384 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_memory_reg1 3 MEM M4K_X13_Y11 0 " "Info: 3: + IC(3.458 ns) + CELL(0.708 ns) = 6.384 ns; Loc. = M4K_X13_Y11; Fanout = 0; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_memory_reg1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.166 ns" { and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } "NODE_NAME" } } { "db/altsyncram_eui2.tdf" "" { Text "E:/lgQ/EDA/peda/sin/db/altsyncram_eui2.tdf" 150 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.822 ns ( 12.88 % ) " "Info: Total cell delay = 0.822 ns ( 12.88 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.562 ns ( 87.12 % ) " "Info: Total interconnect delay = 5.562 ns ( 87.12 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.384 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.384 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } { 0.000ns 2.104ns 3.458ns } { 0.000ns 0.114ns 0.708ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "pll1:u6\|altpll:altpll_component\|_clk0 source 6.398 ns - Longest memory " "Info: - Longest clock path from clock \"pll1:u6\|altpll:altpll_component\|_clk0\" to source memory is 6.398 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pll1:u6\|altpll:altpll_component\|_clk0 1 CLK PLL_1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 1; CLK Node = 'pll1:u6\|altpll:altpll_component\|_clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { pll1:u6|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "c:/altera/quartus60/libraries/megafunctions/altpll.tdf" 767 3 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.104 ns) + CELL(0.114 ns) 2.218 ns and2ab:u7\|clock0 2 COMB LC_X8_Y6_N9 100 " "Info: 2: + IC(2.104 ns) + CELL(0.114 ns) = 2.218 ns; Loc. = LC_X8_Y6_N9; Fanout = 100; COMB Node = 'and2ab:u7\|clock0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.218 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 } "NODE_NAME" } } { "and2ab.vhd" "" { Text "E:/lgQ/EDA/peda/sin/and2ab.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(3.458 ns) + CELL(0.722 ns) 6.398 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_datain_reg1 3 MEM M4K_X13_Y11 1 " "Info: 3: + IC(3.458 ns) + CELL(0.722 ns) = 6.398 ns; Loc. = M4K_X13_Y11; Fanout = 1; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_datain_reg1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.180 ns" { and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_eui2.tdf" "" { Text "E:/lgQ/EDA/peda/sin/db/altsyncram_eui2.tdf" 150 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.836 ns ( 13.07 % ) " "Info: Total cell delay = 0.836 ns ( 13.07 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.562 ns ( 86.93 % ) " "Info: Total interconnect delay = 5.562 ns ( 86.93 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.398 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.398 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 } { 0.000ns 2.104ns 3.458ns } { 0.000ns 0.114ns 0.722ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.384 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.384 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } { 0.000ns 2.104ns 3.458ns } { 0.000ns 0.114ns 0.708ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.398 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.398 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 } { 0.000ns 2.104ns 3.458ns } { 0.000ns 0.114ns 0.722ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.650 ns - " "Info: - Micro clock to output delay of source is 0.650 ns" {  } { { "db/altsyncram_eui2.tdf" "" { Text "E:/lgQ/EDA/peda/sin/db/altsyncram_eui2.tdf" 150 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.093 ns - " "Info: - Micro setup delay of destination is 0.093 ns" {  } { { "db/altsyncram_eui2.tdf" "" { Text "E:/lgQ/EDA/peda/sin/db/altsyncram_eui2.tdf" 150 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.384 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.384 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } { 0.000ns 2.104ns 3.458ns } { 0.000ns 0.114ns 0.708ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.398 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.398 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 } { 0.000ns 2.104ns 3.458ns } { 0.000ns 0.114ns 0.722ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.319 ns - Longest memory memory " "Info: - Longest memory to memory delay is 4.319 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_datain_reg1 1 MEM M4K_X13_Y11 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X13_Y11; Fanout = 1; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_datain_reg1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 } "NODE_NAME" } } { "db/altsyncram_eui2.tdf" "" { Text "E:/lgQ/EDA/peda/sin/db/altsyncram_eui2.tdf" 150 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(4.319 ns) 4.319 ns sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_memory_reg1 2 MEM M4K_X13_Y11 0 " "Info: 2: + IC(0.000 ns) + CELL(4.319 ns) = 4.319 ns; Loc. = M4K_X13_Y11; Fanout = 0; MEM Node = 'sin_rom:u3\|altsyncram:altsyncram_component\|altsyncram_o351:auto_generated\|altsyncram_eui2:altsyncram1\|ram_block3a3~porta_memory_reg1'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } "NODE_NAME" } } { "db/altsyncram_eui2.tdf" "" { Text "E:/lgQ/EDA/peda/sin/db/altsyncram_eui2.tdf" 150 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.319 ns ( 100.00 % ) " "Info: Total cell delay = 4.319 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.384 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.384 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } { 0.000ns 2.104ns 3.458ns } { 0.000ns 0.114ns 0.708ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.398 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.398 ns" { pll1:u6|altpll:altpll_component|_clk0 and2ab:u7|clock0 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 } { 0.000ns 2.104ns 3.458ns } { 0.000ns 0.114ns 0.722ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.319 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.319 ns" { sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 } { 0.000ns 0.000ns } { 0.000ns 4.319ns } } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk " "Info: No valid register-to-register data paths exist for clock \"clk\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}