dds_vhdl.tan.summary

来自「基于fpga的正弦波发生器设计」· SUMMARY 代码 · 共 107 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 5.301 ns
From           : fword[9]
To             : reg32b:u2|dout[31]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 10.334 ns
From           : sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|q_a[4]
To             : fout[4]
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.858 ns
From           : altera_internal_jtag
To             : sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[9]
From Clock     : --
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Worst-case Minimum tco
Slack          : N/A
Required Time  : None
Actual Time    : 4.234 ns
From           : pll1:u6|altpll:altpll_component|_clk0
To             : as
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case Minimum tpd
Slack          : N/A
Required Time  : None
Actual Time    : 2.124 ns
From           : altera_internal_jtag~TDO
To             : altera_reserved_tdo
From Clock     : --
To Clock       : --
Failed Paths   : 0

Type           : Clock Setup: 'pll1:u6|altpll:altpll_component|_clk0'
Slack          : 9.924 ns
Required Time  : 66.67 MHz ( period = 15.000 ns )
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1
To             : sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1
From Clock     : pll1:u6|altpll:altpll_component|_clk0
To Clock       : pll1:u6|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Clock Setup: 'altera_internal_jtag~TCKUTAP'
Slack          : N/A
Required Time  : None
Actual Time    : 93.18 MHz ( period = 10.732 ns )
From           : sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]
To             : sld_hub:sld_hub_inst|hub_tdo
From Clock     : altera_internal_jtag~TCKUTAP
To Clock       : altera_internal_jtag~TCKUTAP
Failed Paths   : 0

Type           : Clock Hold: 'pll1:u6|altpll:altpll_component|_clk0'
Slack          : 1.314 ns
Required Time  : 66.67 MHz ( period = 15.000 ns )
Actual Time    : N/A
From           : reg32b:u2|dout[28]
To             : reg32b:u2|dout[28]
From Clock     : pll1:u6|altpll:altpll_component|_clk0
To Clock       : pll1:u6|altpll:altpll_component|_clk0
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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