adder10b.vhd

基于fpga的正弦波发生器设计

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder10b is
	port(	a,b:	in	std_logic_vector(9 downto 0);
		 	s:	    out	std_logic_vector(9 downto 0));
end adder10b;
architecture behav of adder10b is
	begin
	s<=a+b;
end behav;