dds_vhdl.tan.rpt

来自「基于fpga的正弦波发生器设计」· RPT 代码 · 共 196 行 · 第 1/5 页

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+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                                                                                                                                                                                                                            ;
+------------------------------------------------------+----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+--------------+
; Type                                                 ; Slack    ; Required Time                    ; Actual Time                      ; From                                                                                                                                 ; To                                                                                                                                   ; From Clock                            ; To Clock                              ; Failed Paths ;
+------------------------------------------------------+----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+--------------+
; Worst-case tsu                                       ; N/A      ; None                             ; 5.301 ns                         ; fword[9]                                                                                                                             ; reg32b:u2|dout[31]                                                                                                                   ; --                                    ; clk                                   ; 0            ;
; Worst-case tco                                       ; N/A      ; None                             ; 10.334 ns                        ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|q_a[4]                         ; fout[4]                                                                                                                              ; clk                                   ; --                                    ; 0            ;
; Worst-case tpd                                       ; N/A      ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                             ; altera_reserved_tdo                                                                                                                  ; --                                    ; --                                    ; 0            ;
; Worst-case th                                        ; N/A      ; None                             ; 2.858 ns                         ; altera_internal_jtag                                                                                                                 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[9]              ; --                                    ; altera_internal_jtag~TCKUTAP          ; 0            ;
; Worst-case Minimum tco                               ; N/A      ; None                             ; 4.234 ns                         ; pll1:u6|altpll:altpll_component|_clk0                                                                                                ; as                                                                                                                                   ; clk                                   ; --                                    ; 0            ;
; Worst-case Minimum tpd                               ; N/A      ; None                             ; 2.124 ns                         ; altera_internal_jtag~TDO                                                                                                             ; altera_reserved_tdo                                                                                                                  ; --                                    ; --                                    ; 0            ;
; Clock Setup: 'pll1:u6|altpll:altpll_component|_clk0' ; 9.924 ns ; 66.67 MHz ( period = 15.000 ns ) ; 197.01 MHz ( period = 5.076 ns ) ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_datain_reg1 ; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ram_block3a3~porta_memory_reg1 ; pll1:u6|altpll:altpll_component|_clk0 ; pll1:u6|altpll:altpll_component|_clk0 ; 0            ;
; Clock Setup: 'altera_internal_jtag~TCKUTAP'          ; N/A      ; None                             ; 93.18 MHz ( period = 10.732 ns ) ; sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[1]                                                                                   ; sld_hub:sld_hub_inst|hub_tdo                                                                                                         ; altera_internal_jtag~TCKUTAP          ; altera_internal_jtag~TCKUTAP          ; 0            ;
; Clock Hold: 'pll1:u6|altpll:altpll_component|_clk0'  ; 1.314 ns ; 66.67 MHz ( period = 15.000 ns ) ; N/A                              ; reg32b:u2|dout[28]                                                                                                                   ; reg32b:u2|dout[28]                                                                                                                   ; pll1:u6|altpll:altpll_component|_clk0 ; pll1:u6|altpll:altpll_component|_clk0 ; 0            ;
; Total number of failed paths                         ;          ;                                  ;                                  ;                                                                                                                                      ;                                                                                                                                      ;                                       ;                                       ; 0            ;
+------------------------------------------------------+----------+----------------------------------+----------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+--------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------+---------------------------------------+--------------+


+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                             ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                ; Setting            ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                           ; EP1C3T144C8        ;      ;    ;             ;
; Timing Models                                         ; Final              ;      ;    ;             ;
; Number of source nodes to report per destination node ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                 ; 10                 ;      ;    ;             ;
; Number of paths to report                             ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                          ; On                 ;      ;    ;             ;
; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same As Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;